amd64_edac.c (2a28ceef00bac65d6bb1757002f742806837e100) amd64_edac.c (61810096de3c3ec977c71dbb7e00447d70045163)
1// SPDX-License-Identifier: GPL-2.0-only
2#include "amd64_edac.h"
3#include <asm/amd_nb.h>
4
5static struct edac_pci_ctl_info *pci_ctl;
6
7/*
8 * Set by command line parameter. If BIOS has enabled the ECC, this override is

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602 &dev_attr_topmem2.attr,
603 &dev_attr_dram_hole.attr,
604 NULL
605};
606
607static const struct attribute_group dbg_group = {
608 .attrs = dbg_attrs,
609};
1// SPDX-License-Identifier: GPL-2.0-only
2#include "amd64_edac.h"
3#include <asm/amd_nb.h>
4
5static struct edac_pci_ctl_info *pci_ctl;
6
7/*
8 * Set by command line parameter. If BIOS has enabled the ECC, this override is

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602 &dev_attr_topmem2.attr,
603 &dev_attr_dram_hole.attr,
604 NULL
605};
606
607static const struct attribute_group dbg_group = {
608 .attrs = dbg_attrs,
609};
610#endif /* CONFIG_EDAC_DEBUG */
611
610
611static ssize_t inject_section_show(struct device *dev,
612 struct device_attribute *mattr, char *buf)
613{
614 struct mem_ctl_info *mci = to_mci(dev);
615 struct amd64_pvt *pvt = mci->pvt_info;
616 return sprintf(buf, "0x%x\n", pvt->injection.section);
617}
612
613/*
618
619/*
620 * store error injection section value which refers to one of 4 16-byte sections
621 * within a 64-byte cacheline
622 *
623 * range: 0..3
624 */
625static ssize_t inject_section_store(struct device *dev,
626 struct device_attribute *mattr,
627 const char *data, size_t count)
628{
629 struct mem_ctl_info *mci = to_mci(dev);
630 struct amd64_pvt *pvt = mci->pvt_info;
631 unsigned long value;
632 int ret;
633
634 ret = kstrtoul(data, 10, &value);
635 if (ret < 0)
636 return ret;
637
638 if (value > 3) {
639 amd64_warn("%s: invalid section 0x%lx\n", __func__, value);
640 return -EINVAL;
641 }
642
643 pvt->injection.section = (u32) value;
644 return count;
645}
646
647static ssize_t inject_word_show(struct device *dev,
648 struct device_attribute *mattr, char *buf)
649{
650 struct mem_ctl_info *mci = to_mci(dev);
651 struct amd64_pvt *pvt = mci->pvt_info;
652 return sprintf(buf, "0x%x\n", pvt->injection.word);
653}
654
655/*
656 * store error injection word value which refers to one of 9 16-bit word of the
657 * 16-byte (128-bit + ECC bits) section
658 *
659 * range: 0..8
660 */
661static ssize_t inject_word_store(struct device *dev,
662 struct device_attribute *mattr,
663 const char *data, size_t count)
664{
665 struct mem_ctl_info *mci = to_mci(dev);
666 struct amd64_pvt *pvt = mci->pvt_info;
667 unsigned long value;
668 int ret;
669
670 ret = kstrtoul(data, 10, &value);
671 if (ret < 0)
672 return ret;
673
674 if (value > 8) {
675 amd64_warn("%s: invalid word 0x%lx\n", __func__, value);
676 return -EINVAL;
677 }
678
679 pvt->injection.word = (u32) value;
680 return count;
681}
682
683static ssize_t inject_ecc_vector_show(struct device *dev,
684 struct device_attribute *mattr,
685 char *buf)
686{
687 struct mem_ctl_info *mci = to_mci(dev);
688 struct amd64_pvt *pvt = mci->pvt_info;
689 return sprintf(buf, "0x%x\n", pvt->injection.bit_map);
690}
691
692/*
693 * store 16 bit error injection vector which enables injecting errors to the
694 * corresponding bit within the error injection word above. When used during a
695 * DRAM ECC read, it holds the contents of the of the DRAM ECC bits.
696 */
697static ssize_t inject_ecc_vector_store(struct device *dev,
698 struct device_attribute *mattr,
699 const char *data, size_t count)
700{
701 struct mem_ctl_info *mci = to_mci(dev);
702 struct amd64_pvt *pvt = mci->pvt_info;
703 unsigned long value;
704 int ret;
705
706 ret = kstrtoul(data, 16, &value);
707 if (ret < 0)
708 return ret;
709
710 if (value & 0xFFFF0000) {
711 amd64_warn("%s: invalid EccVector: 0x%lx\n", __func__, value);
712 return -EINVAL;
713 }
714
715 pvt->injection.bit_map = (u32) value;
716 return count;
717}
718
719/*
720 * Do a DRAM ECC read. Assemble staged values in the pvt area, format into
721 * fields needed by the injection registers and read the NB Array Data Port.
722 */
723static ssize_t inject_read_store(struct device *dev,
724 struct device_attribute *mattr,
725 const char *data, size_t count)
726{
727 struct mem_ctl_info *mci = to_mci(dev);
728 struct amd64_pvt *pvt = mci->pvt_info;
729 unsigned long value;
730 u32 section, word_bits;
731 int ret;
732
733 ret = kstrtoul(data, 10, &value);
734 if (ret < 0)
735 return ret;
736
737 /* Form value to choose 16-byte section of cacheline */
738 section = F10_NB_ARRAY_DRAM | SET_NB_ARRAY_ADDR(pvt->injection.section);
739
740 amd64_write_pci_cfg(pvt->F3, F10_NB_ARRAY_ADDR, section);
741
742 word_bits = SET_NB_DRAM_INJECTION_READ(pvt->injection);
743
744 /* Issue 'word' and 'bit' along with the READ request */
745 amd64_write_pci_cfg(pvt->F3, F10_NB_ARRAY_DATA, word_bits);
746
747 edac_dbg(0, "section=0x%x word_bits=0x%x\n", section, word_bits);
748
749 return count;
750}
751
752/*
753 * Do a DRAM ECC write. Assemble staged values in the pvt area and format into
754 * fields needed by the injection registers.
755 */
756static ssize_t inject_write_store(struct device *dev,
757 struct device_attribute *mattr,
758 const char *data, size_t count)
759{
760 struct mem_ctl_info *mci = to_mci(dev);
761 struct amd64_pvt *pvt = mci->pvt_info;
762 u32 section, word_bits, tmp;
763 unsigned long value;
764 int ret;
765
766 ret = kstrtoul(data, 10, &value);
767 if (ret < 0)
768 return ret;
769
770 /* Form value to choose 16-byte section of cacheline */
771 section = F10_NB_ARRAY_DRAM | SET_NB_ARRAY_ADDR(pvt->injection.section);
772
773 amd64_write_pci_cfg(pvt->F3, F10_NB_ARRAY_ADDR, section);
774
775 word_bits = SET_NB_DRAM_INJECTION_WRITE(pvt->injection);
776
777 pr_notice_once("Don't forget to decrease MCE polling interval in\n"
778 "/sys/bus/machinecheck/devices/machinecheck<CPUNUM>/check_interval\n"
779 "so that you can get the error report faster.\n");
780
781 on_each_cpu(disable_caches, NULL, 1);
782
783 /* Issue 'word' and 'bit' along with the READ request */
784 amd64_write_pci_cfg(pvt->F3, F10_NB_ARRAY_DATA, word_bits);
785
786 retry:
787 /* wait until injection happens */
788 amd64_read_pci_cfg(pvt->F3, F10_NB_ARRAY_DATA, &tmp);
789 if (tmp & F10_NB_ARR_ECC_WR_REQ) {
790 cpu_relax();
791 goto retry;
792 }
793
794 on_each_cpu(enable_caches, NULL, 1);
795
796 edac_dbg(0, "section=0x%x word_bits=0x%x\n", section, word_bits);
797
798 return count;
799}
800
801/*
802 * update NUM_INJ_ATTRS in case you add new members
803 */
804
805static DEVICE_ATTR(inject_section, S_IRUGO | S_IWUSR,
806 inject_section_show, inject_section_store);
807static DEVICE_ATTR(inject_word, S_IRUGO | S_IWUSR,
808 inject_word_show, inject_word_store);
809static DEVICE_ATTR(inject_ecc_vector, S_IRUGO | S_IWUSR,
810 inject_ecc_vector_show, inject_ecc_vector_store);
811static DEVICE_ATTR(inject_write, S_IWUSR,
812 NULL, inject_write_store);
813static DEVICE_ATTR(inject_read, S_IWUSR,
814 NULL, inject_read_store);
815
816static struct attribute *inj_attrs[] = {
817 &dev_attr_inject_section.attr,
818 &dev_attr_inject_word.attr,
819 &dev_attr_inject_ecc_vector.attr,
820 &dev_attr_inject_write.attr,
821 &dev_attr_inject_read.attr,
822 NULL
823};
824
825static umode_t inj_is_visible(struct kobject *kobj, struct attribute *attr, int idx)
826{
827 struct device *dev = kobj_to_dev(kobj);
828 struct mem_ctl_info *mci = container_of(dev, struct mem_ctl_info, dev);
829 struct amd64_pvt *pvt = mci->pvt_info;
830
831 if (pvt->fam < 0x10)
832 return 0;
833 return attr->mode;
834}
835
836static const struct attribute_group inj_group = {
837 .attrs = inj_attrs,
838 .is_visible = inj_is_visible,
839};
840#endif /* CONFIG_EDAC_DEBUG */
841
842/*
614 * Return the DramAddr that the SysAddr given by @sys_addr maps to. It is
615 * assumed that sys_addr maps to the node given by mci.
616 *
617 * The first part of section 3.4.4 (p. 70) shows how the DRAM Base (section
618 * 3.4.4.1) and DRAM Limit (section 3.4.4.2) registers are used to translate a
619 * SysAddr to a DramAddr. If the DRAM Hole Address Register (DHAR) is enabled,
620 * then it is also involved in translating a SysAddr to a DramAddr. Sections
621 * 3.4.8 and 3.5.8.2 describe the DHAR and how it is used for memory hoisting.

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3464 : "revE or earlier ")
3465 : ""), pvt->mc_node_id);
3466 return fam_type;
3467}
3468
3469static const struct attribute_group *amd64_edac_attr_groups[] = {
3470#ifdef CONFIG_EDAC_DEBUG
3471 &dbg_group,
843 * Return the DramAddr that the SysAddr given by @sys_addr maps to. It is
844 * assumed that sys_addr maps to the node given by mci.
845 *
846 * The first part of section 3.4.4 (p. 70) shows how the DRAM Base (section
847 * 3.4.4.1) and DRAM Limit (section 3.4.4.2) registers are used to translate a
848 * SysAddr to a DramAddr. If the DRAM Hole Address Register (DHAR) is enabled,
849 * then it is also involved in translating a SysAddr to a DramAddr. Sections
850 * 3.4.8 and 3.5.8.2 describe the DHAR and how it is used for memory hoisting.

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3693 : "revE or earlier ")
3694 : ""), pvt->mc_node_id);
3695 return fam_type;
3696}
3697
3698static const struct attribute_group *amd64_edac_attr_groups[] = {
3699#ifdef CONFIG_EDAC_DEBUG
3700 &dbg_group,
3701 &inj_group,
3472#endif
3702#endif
3473#ifdef CONFIG_EDAC_AMD64_ERROR_INJECTION
3474 &amd64_edac_inj_group,
3475#endif
3476 NULL
3477};
3478
3479static int hw_info_get(struct amd64_pvt *pvt)
3480{
3481 u16 pci_id1, pci_id2;
3482 int ret;
3483

--- 330 unchanged lines hidden --- 		3703 NULL
3704};
3705
3706static int hw_info_get(struct amd64_pvt *pvt)
3707{
3708 u16 pci_id1, pci_id2;
3709 int ret;
3710

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