altera_edac.c (a2071cd765637002523798358d2ca441306d708b) | altera_edac.c (911049845d7096c27304930ff478cbf3f2623ba3) |
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1/* 2 * Copyright Altera Corporation (C) 2014-2016. All rights reserved. 3 * Copyright 2011-2012 Calxeda, Inc. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms and conditions of the GNU General Public License, 7 * version 2, as published by the Free Software Foundation. 8 * --- 1271 unchanged lines hidden (view full) --- 1280{ 1281 return altr_init_a10_ecc_device_type("altr,socfpga-eth-mac-ecc"); 1282} 1283 1284early_initcall(socfpga_init_ethernet_ecc); 1285 1286#endif /* CONFIG_EDAC_ALTERA_ETHERNET */ 1287 | 1/* 2 * Copyright Altera Corporation (C) 2014-2016. All rights reserved. 3 * Copyright 2011-2012 Calxeda, Inc. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms and conditions of the GNU General Public License, 7 * version 2, as published by the Free Software Foundation. 8 * --- 1271 unchanged lines hidden (view full) --- 1280{ 1281 return altr_init_a10_ecc_device_type("altr,socfpga-eth-mac-ecc"); 1282} 1283 1284early_initcall(socfpga_init_ethernet_ecc); 1285 1286#endif /* CONFIG_EDAC_ALTERA_ETHERNET */ 1287 |
1288/********************** NAND Device Functions **********************/ 1289 1290#ifdef CONFIG_EDAC_ALTERA_NAND 1291 1292static const struct edac_device_prv_data a10_nandecc_data = { 1293 .setup = altr_check_ecc_deps, 1294 .ce_clear_mask = ALTR_A10_ECC_SERRPENA, 1295 .ue_clear_mask = ALTR_A10_ECC_DERRPENA, 1296 .dbgfs_name = "altr_trigger", 1297 .ecc_enable_mask = ALTR_A10_COMMON_ECC_EN_CTL, 1298 .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST, 1299 .ce_set_mask = ALTR_A10_ECC_TSERRA, 1300 .ue_set_mask = ALTR_A10_ECC_TDERRA, 1301 .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST, 1302 .ecc_irq_handler = altr_edac_a10_ecc_irq, 1303 .inject_fops = &altr_edac_a10_device_inject_fops, 1304}; 1305 1306static int __init socfpga_init_nand_ecc(void) 1307{ 1308 return altr_init_a10_ecc_device_type("altr,socfpga-nand-ecc"); 1309} 1310 1311early_initcall(socfpga_init_nand_ecc); 1312 1313#endif /* CONFIG_EDAC_ALTERA_NAND */ 1314 1315/********************** DMA Device Functions **********************/ 1316 1317#ifdef CONFIG_EDAC_ALTERA_DMA 1318 1319static const struct edac_device_prv_data a10_dmaecc_data = { 1320 .setup = altr_check_ecc_deps, 1321 .ce_clear_mask = ALTR_A10_ECC_SERRPENA, 1322 .ue_clear_mask = ALTR_A10_ECC_DERRPENA, 1323 .dbgfs_name = "altr_trigger", 1324 .ecc_enable_mask = ALTR_A10_COMMON_ECC_EN_CTL, 1325 .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST, 1326 .ce_set_mask = ALTR_A10_ECC_TSERRA, 1327 .ue_set_mask = ALTR_A10_ECC_TDERRA, 1328 .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST, 1329 .ecc_irq_handler = altr_edac_a10_ecc_irq, 1330 .inject_fops = &altr_edac_a10_device_inject_fops, 1331}; 1332 1333static int __init socfpga_init_dma_ecc(void) 1334{ 1335 return altr_init_a10_ecc_device_type("altr,socfpga-dma-ecc"); 1336} 1337 1338early_initcall(socfpga_init_dma_ecc); 1339 1340#endif /* CONFIG_EDAC_ALTERA_DMA */ 1341 1342/********************** USB Device Functions **********************/ 1343 1344#ifdef CONFIG_EDAC_ALTERA_USB 1345 1346static const struct edac_device_prv_data a10_usbecc_data = { 1347 .setup = altr_check_ecc_deps, 1348 .ce_clear_mask = ALTR_A10_ECC_SERRPENA, 1349 .ue_clear_mask = ALTR_A10_ECC_DERRPENA, 1350 .dbgfs_name = "altr_trigger", 1351 .ecc_enable_mask = ALTR_A10_COMMON_ECC_EN_CTL, 1352 .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST, 1353 .ce_set_mask = ALTR_A10_ECC_TSERRA, 1354 .ue_set_mask = ALTR_A10_ECC_TDERRA, 1355 .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST, 1356 .ecc_irq_handler = altr_edac_a10_ecc_irq, 1357 .inject_fops = &altr_edac_a10_device_inject_fops, 1358}; 1359 1360static int __init socfpga_init_usb_ecc(void) 1361{ 1362 return altr_init_a10_ecc_device_type("altr,socfpga-usb-ecc"); 1363} 1364 1365early_initcall(socfpga_init_usb_ecc); 1366 1367#endif /* CONFIG_EDAC_ALTERA_USB */ 1368 1369/********************** QSPI Device Functions **********************/ 1370 1371#ifdef CONFIG_EDAC_ALTERA_QSPI 1372 1373static const struct edac_device_prv_data a10_qspiecc_data = { 1374 .setup = altr_check_ecc_deps, 1375 .ce_clear_mask = ALTR_A10_ECC_SERRPENA, 1376 .ue_clear_mask = ALTR_A10_ECC_DERRPENA, 1377 .dbgfs_name = "altr_trigger", 1378 .ecc_enable_mask = ALTR_A10_COMMON_ECC_EN_CTL, 1379 .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST, 1380 .ce_set_mask = ALTR_A10_ECC_TSERRA, 1381 .ue_set_mask = ALTR_A10_ECC_TDERRA, 1382 .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST, 1383 .ecc_irq_handler = altr_edac_a10_ecc_irq, 1384 .inject_fops = &altr_edac_a10_device_inject_fops, 1385}; 1386 1387static int __init socfpga_init_qspi_ecc(void) 1388{ 1389 return altr_init_a10_ecc_device_type("altr,socfpga-qspi-ecc"); 1390} 1391 1392early_initcall(socfpga_init_qspi_ecc); 1393 1394#endif /* CONFIG_EDAC_ALTERA_QSPI */ 1395 1396/********************* SDMMC Device Functions **********************/ 1397 1398#ifdef CONFIG_EDAC_ALTERA_SDMMC 1399 1400static const struct edac_device_prv_data a10_sdmmceccb_data; 1401static int altr_portb_setup(struct altr_edac_device_dev *device) 1402{ 1403 struct edac_device_ctl_info *dci; 1404 struct altr_edac_device_dev *altdev; 1405 char *ecc_name = "sdmmcb-ecc"; 1406 int edac_idx, rc; 1407 struct device_node *np; 1408 const struct edac_device_prv_data *prv = &a10_sdmmceccb_data; 1409 1410 rc = altr_check_ecc_deps(device); 1411 if (rc) 1412 return rc; 1413 1414 np = of_find_compatible_node(NULL, NULL, "altr,socfpga-sdmmc-ecc"); 1415 if (!np) { 1416 edac_printk(KERN_WARNING, EDAC_DEVICE, "SDMMC node not found\n"); 1417 return -ENODEV; 1418 } 1419 1420 /* Create the PortB EDAC device */ 1421 edac_idx = edac_device_alloc_index(); 1422 dci = edac_device_alloc_ctl_info(sizeof(*altdev), ecc_name, 1, 1423 ecc_name, 1, 0, NULL, 0, edac_idx); 1424 if (!dci) { 1425 edac_printk(KERN_ERR, EDAC_DEVICE, 1426 "%s: Unable to allocate PortB EDAC device\n", 1427 ecc_name); 1428 return -ENOMEM; 1429 } 1430 1431 /* Initialize the PortB EDAC device structure from PortA structure */ 1432 altdev = dci->pvt_info; 1433 *altdev = *device; 1434 1435 if (!devres_open_group(&altdev->ddev, altr_portb_setup, GFP_KERNEL)) 1436 return -ENOMEM; 1437 1438 /* Update PortB specific values */ 1439 altdev->edac_dev_name = ecc_name; 1440 altdev->edac_idx = edac_idx; 1441 altdev->edac_dev = dci; 1442 altdev->data = prv; 1443 dci->dev = &altdev->ddev; 1444 dci->ctl_name = "Altera ECC Manager"; 1445 dci->mod_name = ecc_name; 1446 dci->dev_name = ecc_name; 1447 1448 /* Update the IRQs for PortB */ 1449 altdev->sb_irq = irq_of_parse_and_map(np, 2); 1450 if (!altdev->sb_irq) { 1451 edac_printk(KERN_ERR, EDAC_DEVICE, "Error PortB SBIRQ alloc\n"); 1452 rc = -ENODEV; 1453 goto err_release_group_1; 1454 } 1455 rc = devm_request_irq(&altdev->ddev, altdev->sb_irq, 1456 prv->ecc_irq_handler, 1457 IRQF_SHARED, ecc_name, altdev); 1458 if (rc) { 1459 edac_printk(KERN_ERR, EDAC_DEVICE, "PortB SBERR IRQ error\n"); 1460 goto err_release_group_1; 1461 } 1462 1463 altdev->db_irq = irq_of_parse_and_map(np, 3); 1464 if (!altdev->db_irq) { 1465 edac_printk(KERN_ERR, EDAC_DEVICE, "Error PortB DBIRQ alloc\n"); 1466 rc = -ENODEV; 1467 goto err_release_group_1; 1468 } 1469 rc = devm_request_irq(&altdev->ddev, altdev->db_irq, 1470 prv->ecc_irq_handler, 1471 IRQF_SHARED, ecc_name, altdev); 1472 if (rc) { 1473 edac_printk(KERN_ERR, EDAC_DEVICE, "PortB DBERR IRQ error\n"); 1474 goto err_release_group_1; 1475 } 1476 1477 rc = edac_device_add_device(dci); 1478 if (rc) { 1479 edac_printk(KERN_ERR, EDAC_DEVICE, 1480 "edac_device_add_device portB failed\n"); 1481 rc = -ENOMEM; 1482 goto err_release_group_1; 1483 } 1484 altr_create_edacdev_dbgfs(dci, prv); 1485 1486 list_add(&altdev->next, &altdev->edac->a10_ecc_devices); 1487 1488 devres_remove_group(&altdev->ddev, altr_portb_setup); 1489 1490 return 0; 1491 1492err_release_group_1: 1493 edac_device_free_ctl_info(dci); 1494 devres_release_group(&altdev->ddev, altr_portb_setup); 1495 edac_printk(KERN_ERR, EDAC_DEVICE, 1496 "%s:Error setting up EDAC device: %d\n", ecc_name, rc); 1497 return rc; 1498} 1499 1500static irqreturn_t altr_edac_a10_ecc_irq_portb(int irq, void *dev_id) 1501{ 1502 struct altr_edac_device_dev *ad = dev_id; 1503 void __iomem *base = ad->base; 1504 const struct edac_device_prv_data *priv = ad->data; 1505 1506 if (irq == ad->sb_irq) { 1507 writel(priv->ce_clear_mask, 1508 base + ALTR_A10_ECC_INTSTAT_OFST); 1509 edac_device_handle_ce(ad->edac_dev, 0, 0, ad->edac_dev_name); 1510 return IRQ_HANDLED; 1511 } else if (irq == ad->db_irq) { 1512 writel(priv->ue_clear_mask, 1513 base + ALTR_A10_ECC_INTSTAT_OFST); 1514 edac_device_handle_ue(ad->edac_dev, 0, 0, ad->edac_dev_name); 1515 return IRQ_HANDLED; 1516 } 1517 1518 WARN_ONCE(1, "Unhandled IRQ%d on Port B.", irq); 1519 1520 return IRQ_NONE; 1521} 1522 1523static const struct edac_device_prv_data a10_sdmmcecca_data = { 1524 .setup = altr_portb_setup, 1525 .ce_clear_mask = ALTR_A10_ECC_SERRPENA, 1526 .ue_clear_mask = ALTR_A10_ECC_DERRPENA, 1527 .dbgfs_name = "altr_trigger", 1528 .ecc_enable_mask = ALTR_A10_COMMON_ECC_EN_CTL, 1529 .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST, 1530 .ce_set_mask = ALTR_A10_ECC_SERRPENA, 1531 .ue_set_mask = ALTR_A10_ECC_DERRPENA, 1532 .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST, 1533 .ecc_irq_handler = altr_edac_a10_ecc_irq, 1534 .inject_fops = &altr_edac_a10_device_inject_fops, 1535}; 1536 1537static const struct edac_device_prv_data a10_sdmmceccb_data = { 1538 .setup = altr_portb_setup, 1539 .ce_clear_mask = ALTR_A10_ECC_SERRPENB, 1540 .ue_clear_mask = ALTR_A10_ECC_DERRPENB, 1541 .dbgfs_name = "altr_trigger", 1542 .ecc_enable_mask = ALTR_A10_COMMON_ECC_EN_CTL, 1543 .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST, 1544 .ce_set_mask = ALTR_A10_ECC_TSERRB, 1545 .ue_set_mask = ALTR_A10_ECC_TDERRB, 1546 .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST, 1547 .ecc_irq_handler = altr_edac_a10_ecc_irq_portb, 1548 .inject_fops = &altr_edac_a10_device_inject_fops, 1549}; 1550 1551static int __init socfpga_init_sdmmc_ecc(void) 1552{ 1553 int rc = -ENODEV; 1554 struct device_node *child = of_find_compatible_node(NULL, NULL, 1555 "altr,socfpga-sdmmc-ecc"); 1556 if (!child) { 1557 edac_printk(KERN_WARNING, EDAC_DEVICE, "SDMMC node not found\n"); 1558 return -ENODEV; 1559 } 1560 1561 if (!of_device_is_available(child)) 1562 goto exit; 1563 1564 if (validate_parent_available(child)) 1565 goto exit; 1566 1567 rc = altr_init_a10_ecc_block(child, ALTR_A10_SDMMC_IRQ_MASK, 1568 a10_sdmmcecca_data.ecc_enable_mask, 1); 1569exit: 1570 of_node_put(child); 1571 return rc; 1572} 1573 1574early_initcall(socfpga_init_sdmmc_ecc); 1575 1576#endif /* CONFIG_EDAC_ALTERA_SDMMC */ 1577 |
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1288/********************* Arria10 EDAC Device Functions *************************/ 1289static const struct of_device_id altr_edac_a10_device_of_match[] = { 1290#ifdef CONFIG_EDAC_ALTERA_L2C 1291 { .compatible = "altr,socfpga-a10-l2-ecc", .data = &a10_l2ecc_data }, 1292#endif 1293#ifdef CONFIG_EDAC_ALTERA_OCRAM 1294 { .compatible = "altr,socfpga-a10-ocram-ecc", 1295 .data = &a10_ocramecc_data }, 1296#endif 1297#ifdef CONFIG_EDAC_ALTERA_ETHERNET 1298 { .compatible = "altr,socfpga-eth-mac-ecc", 1299 .data = &a10_enetecc_data }, 1300#endif | 1578/********************* Arria10 EDAC Device Functions *************************/ 1579static const struct of_device_id altr_edac_a10_device_of_match[] = { 1580#ifdef CONFIG_EDAC_ALTERA_L2C 1581 { .compatible = "altr,socfpga-a10-l2-ecc", .data = &a10_l2ecc_data }, 1582#endif 1583#ifdef CONFIG_EDAC_ALTERA_OCRAM 1584 { .compatible = "altr,socfpga-a10-ocram-ecc", 1585 .data = &a10_ocramecc_data }, 1586#endif 1587#ifdef CONFIG_EDAC_ALTERA_ETHERNET 1588 { .compatible = "altr,socfpga-eth-mac-ecc", 1589 .data = &a10_enetecc_data }, 1590#endif |
1591#ifdef CONFIG_EDAC_ALTERA_NAND 1592 { .compatible = "altr,socfpga-nand-ecc", .data = &a10_nandecc_data }, 1593#endif 1594#ifdef CONFIG_EDAC_ALTERA_DMA 1595 { .compatible = "altr,socfpga-dma-ecc", .data = &a10_dmaecc_data }, 1596#endif 1597#ifdef CONFIG_EDAC_ALTERA_USB 1598 { .compatible = "altr,socfpga-usb-ecc", .data = &a10_usbecc_data }, 1599#endif 1600#ifdef CONFIG_EDAC_ALTERA_QSPI 1601 { .compatible = "altr,socfpga-qspi-ecc", .data = &a10_qspiecc_data }, 1602#endif 1603#ifdef CONFIG_EDAC_ALTERA_SDMMC 1604 { .compatible = "altr,socfpga-sdmmc-ecc", .data = &a10_sdmmcecca_data }, 1605#endif |
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1301 {}, 1302}; 1303MODULE_DEVICE_TABLE(of, altr_edac_a10_device_of_match); 1304 1305/* 1306 * The Arria10 EDAC Device Functions differ from the Cyclone5/Arria5 1307 * because 2 IRQs are shared among the all ECC peripherals. The ECC 1308 * manager manages the IRQs and the children. --- 270 unchanged lines hidden (view full) --- 1579 } 1580 irq_set_chained_handler_and_data(edac->db_irq, 1581 altr_edac_a10_irq_handler, 1582 edac); 1583 1584 for_each_child_of_node(pdev->dev.of_node, child) { 1585 if (!of_device_is_available(child)) 1586 continue; | 1606 {}, 1607}; 1608MODULE_DEVICE_TABLE(of, altr_edac_a10_device_of_match); 1609 1610/* 1611 * The Arria10 EDAC Device Functions differ from the Cyclone5/Arria5 1612 * because 2 IRQs are shared among the all ECC peripherals. The ECC 1613 * manager manages the IRQs and the children. --- 270 unchanged lines hidden (view full) --- 1884 } 1885 irq_set_chained_handler_and_data(edac->db_irq, 1886 altr_edac_a10_irq_handler, 1887 edac); 1888 1889 for_each_child_of_node(pdev->dev.of_node, child) { 1890 if (!of_device_is_available(child)) 1891 continue; |
1587 if (of_device_is_compatible(child, "altr,socfpga-a10-l2-ecc")) | 1892 1893 if (of_device_is_compatible(child, "altr,socfpga-a10-l2-ecc") || 1894 of_device_is_compatible(child, "altr,socfpga-a10-ocram-ecc") || 1895 of_device_is_compatible(child, "altr,socfpga-eth-mac-ecc") || 1896 of_device_is_compatible(child, "altr,socfpga-nand-ecc") || 1897 of_device_is_compatible(child, "altr,socfpga-dma-ecc") || 1898 of_device_is_compatible(child, "altr,socfpga-usb-ecc") || 1899 of_device_is_compatible(child, "altr,socfpga-qspi-ecc") || 1900 of_device_is_compatible(child, "altr,socfpga-sdmmc-ecc")) 1901 |
1588 altr_edac_a10_device_add(edac, child); | 1902 altr_edac_a10_device_add(edac, child); |
1589 else if ((of_device_is_compatible(child, 1590 "altr,socfpga-a10-ocram-ecc")) || 1591 (of_device_is_compatible(child, 1592 "altr,socfpga-eth-mac-ecc"))) 1593 altr_edac_a10_device_add(edac, child); 1594 else if (of_device_is_compatible(child, 1595 "altr,sdram-edac-a10")) | 1903 1904 else if (of_device_is_compatible(child, "altr,sdram-edac-a10")) |
1596 of_platform_populate(pdev->dev.of_node, 1597 altr_sdram_ctrl_of_match, 1598 NULL, &pdev->dev); 1599 } 1600 1601 return 0; 1602} 1603 --- 18 unchanged lines hidden --- | 1905 of_platform_populate(pdev->dev.of_node, 1906 altr_sdram_ctrl_of_match, 1907 NULL, &pdev->dev); 1908 } 1909 1910 return 0; 1911} 1912 --- 18 unchanged lines hidden --- |