registers.h (58e16d792a6a8c6b750f637a4649967fcac853dc) registers.h (8f6707d0773be31972768abd6e0bf7b8515b5b1a)
1/* SPDX-License-Identifier: GPL-2.0-or-later */
2/*
3 * Copyright(c) 2004 - 2009 Intel Corporation. All rights reserved.
4 */
5#ifndef _IOAT_REGISTERS_H_
6#define _IOAT_REGISTERS_H_
7
8#define IOAT_PCI_DMACTRL_OFFSET 0x48
9#define IOAT_PCI_DMACTRL_DMA_EN 0x00000001
10#define IOAT_PCI_DMACTRL_MSI_EN 0x00000002
11
12#define IOAT_PCI_DEVICE_ID_OFFSET 0x02
13#define IOAT_PCI_DMAUNCERRSTS_OFFSET 0x148
14#define IOAT_PCI_CHANERR_INT_OFFSET 0x180
15#define IOAT_PCI_CHANERRMASK_INT_OFFSET 0x184
16
1/* SPDX-License-Identifier: GPL-2.0-or-later */
2/*
3 * Copyright(c) 2004 - 2009 Intel Corporation. All rights reserved.
4 */
5#ifndef _IOAT_REGISTERS_H_
6#define _IOAT_REGISTERS_H_
7
8#define IOAT_PCI_DMACTRL_OFFSET 0x48
9#define IOAT_PCI_DMACTRL_DMA_EN 0x00000001
10#define IOAT_PCI_DMACTRL_MSI_EN 0x00000002
11
12#define IOAT_PCI_DEVICE_ID_OFFSET 0x02
13#define IOAT_PCI_DMAUNCERRSTS_OFFSET 0x148
14#define IOAT_PCI_CHANERR_INT_OFFSET 0x180
15#define IOAT_PCI_CHANERRMASK_INT_OFFSET 0x184
16
17/* PCIe config registers */
18
19/* EXPCAPID + N */
20#define IOAT_DEVCTRL_OFFSET 0x8
21/* relaxed ordering enable */
22#define IOAT_DEVCTRL_ROE 0x10
23
24/* MMIO Device Registers */
25#define IOAT_CHANCNT_OFFSET 0x00 /* 8-bit */
26
27#define IOAT_XFERCAP_OFFSET 0x01 /* 8-bit */
28#define IOAT_XFERCAP_4KB 12
29#define IOAT_XFERCAP_8KB 13
30#define IOAT_XFERCAP_16KB 14
31#define IOAT_XFERCAP_32KB 15

--- 227 unchanged lines hidden --- 		17/* MMIO Device Registers */
18#define IOAT_CHANCNT_OFFSET 0x00 /* 8-bit */
19
20#define IOAT_XFERCAP_OFFSET 0x01 /* 8-bit */
21#define IOAT_XFERCAP_4KB 12
22#define IOAT_XFERCAP_8KB 13
23#define IOAT_XFERCAP_16KB 14
24#define IOAT_XFERCAP_32KB 15

--- 227 unchanged lines hidden ---