dma.h (3372de5813e4da8305002ff6ffbfc0c7012cb319) dma.h (ef97bd0f59741ca1a555b69b8708f6601e35c3ed)
1/*
2 * Copyright(c) 2004 - 2009 Intel Corporation. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the Free
6 * Software Foundation; either version 2 of the License, or (at your option)
7 * any later version.
8 *

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63 * @pdev: PCI-Express device
64 * @reg_base: MMIO register space base address
65 * @dma_pool: for allocating DMA descriptors
66 * @dma_dev: embedded struct dma_device
67 * @version: version of ioatdma device
68 * @msix_entries: irq handlers
69 * @idx: per channel data
70 * @dca: direct cache access context
1/*
2 * Copyright(c) 2004 - 2009 Intel Corporation. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the Free
6 * Software Foundation; either version 2 of the License, or (at your option)
7 * any later version.
8 *

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63 * @pdev: PCI-Express device
64 * @reg_base: MMIO register space base address
65 * @dma_pool: for allocating DMA descriptors
66 * @dma_dev: embedded struct dma_device
67 * @version: version of ioatdma device
68 * @msix_entries: irq handlers
69 * @idx: per channel data
70 * @dca: direct cache access context
71 * @intr_quirk: interrupt setup quirk (for ioat_v1 devices)
72 * @enumerate_channels: hw version specific channel enumeration
73 * @reset_hw: hw version specific channel (re)initialization
74 * @cleanup_fn: select between the v2 and v3 cleanup routines
75 * @timer_fn: select between the v2 and v3 timer watchdog routines
76 * @self_test: hardware version specific self test for each supported op type
77 *
78 * Note: the v3 cleanup routine supports raid operations
79 */
80struct ioatdma_device {
81 struct pci_dev *pdev;
82 void __iomem *reg_base;
83 struct pci_pool *dma_pool;
84 struct pci_pool *completion_pool;
85#define MAX_SED_POOLS 5
86 struct dma_pool *sed_hw_pool[MAX_SED_POOLS];
87 struct dma_device dma_dev;
88 u8 version;
89 struct msix_entry msix_entries[4];
90 struct ioatdma_chan *idx[4];
91 struct dca_provider *dca;
92 enum ioat_irq_mode irq_mode;
93 u32 cap;
71 */
72struct ioatdma_device {
73 struct pci_dev *pdev;
74 void __iomem *reg_base;
75 struct pci_pool *dma_pool;
76 struct pci_pool *completion_pool;
77#define MAX_SED_POOLS 5
78 struct dma_pool *sed_hw_pool[MAX_SED_POOLS];
79 struct dma_device dma_dev;
80 u8 version;
81 struct msix_entry msix_entries[4];
82 struct ioatdma_chan *idx[4];
83 struct dca_provider *dca;
84 enum ioat_irq_mode irq_mode;
85 u32 cap;
94 void (*intr_quirk)(struct ioatdma_device *ioat_dma);
95 int (*enumerate_channels)(struct ioatdma_device *ioat_dma);
96 int (*reset_hw)(struct ioatdma_chan *ioat_chan);
97 void (*cleanup_fn)(unsigned long data);
98 void (*timer_fn)(unsigned long data);
99 int (*self_test)(struct ioatdma_device *ioat_dma);
100};
101
102struct ioatdma_chan {
103 struct dma_chan dma_chan;
104 void __iomem *reg_base;
105 dma_addr_t last_completion;
106 spinlock_t cleanup_lock;
107 unsigned long state;

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87
88struct ioatdma_chan {
89 struct dma_chan dma_chan;
90 void __iomem *reg_base;
91 dma_addr_t last_completion;
92 spinlock_t cleanup_lock;
93 unsigned long state;

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