dma.c (c0f28ce66ecfd9fa0ae662a2c7f3e68e537e77f4) dma.c (599d49de7f69cb5a23e913db24e168ba2f09bd05)
1/*
2 * Intel I/OAT DMA Linux driver
3 * Copyright(c) 2004 - 2015 Intel Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *

--- 564 unchanged lines hidden (view full) ---

573 struct ioatdma_device *ioat_dma = ioat_chan->ioat_dma;
574
575 mod_timer(&ioat_chan->timer, jiffies + COMPLETION_TIMEOUT);
576 ioat_dma->timer_fn((unsigned long)ioat_chan);
577 }
578
579 return -ENOMEM;
580}
1/*
2 * Intel I/OAT DMA Linux driver
3 * Copyright(c) 2004 - 2015 Intel Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *

--- 564 unchanged lines hidden (view full) ---

573 struct ioatdma_device *ioat_dma = ioat_chan->ioat_dma;
574
575 mod_timer(&ioat_chan->timer, jiffies + COMPLETION_TIMEOUT);
576 ioat_dma->timer_fn((unsigned long)ioat_chan);
577 }
578
579 return -ENOMEM;
580}
581
582struct dma_async_tx_descriptor *
583ioat_dma_prep_memcpy_lock(struct dma_chan *c, dma_addr_t dma_dest,
584 dma_addr_t dma_src, size_t len, unsigned long flags)
585{
586 struct ioatdma_chan *ioat_chan = to_ioat_chan(c);
587 struct ioat_dma_descriptor *hw;
588 struct ioat_ring_ent *desc;
589 dma_addr_t dst = dma_dest;
590 dma_addr_t src = dma_src;
591 size_t total_len = len;
592 int num_descs, idx, i;
593
594 num_descs = ioat_xferlen_to_descs(ioat_chan, len);
595 if (likely(num_descs) &&
596 ioat_check_space_lock(ioat_chan, num_descs) == 0)
597 idx = ioat_chan->head;
598 else
599 return NULL;
600 i = 0;
601 do {
602 size_t copy = min_t(size_t, len, 1 << ioat_chan->xfercap_log);
603
604 desc = ioat_get_ring_ent(ioat_chan, idx + i);
605 hw = desc->hw;
606
607 hw->size = copy;
608 hw->ctl = 0;
609 hw->src_addr = src;
610 hw->dst_addr = dst;
611
612 len -= copy;
613 dst += copy;
614 src += copy;
615 dump_desc_dbg(ioat_chan, desc);
616 } while (++i < num_descs);
617
618 desc->txd.flags = flags;
619 desc->len = total_len;
620 hw->ctl_f.int_en = !!(flags & DMA_PREP_INTERRUPT);
621 hw->ctl_f.fence = !!(flags & DMA_PREP_FENCE);
622 hw->ctl_f.compl_write = 1;
623 dump_desc_dbg(ioat_chan, desc);
624 /* we leave the channel locked to ensure in order submission */
625
626 return &desc->txd;
627}