init.c (fffaed1e24b8d114e958d180cb4a8aed3febbb5a) init.c (34ca00662eb7f184f249dd2168ebea78d945e3e4)
1// SPDX-License-Identifier: GPL-2.0
2/* Copyright(c) 2019 Intel Corporation. All rights rsvd. */
3#include <linux/init.h>
4#include <linux/kernel.h>
5#include <linux/module.h>
6#include <linux/slab.h>
7#include <linux/pci.h>
8#include <linux/interrupt.h>
9#include <linux/delay.h>
10#include <linux/dma-mapping.h>
11#include <linux/workqueue.h>
1// SPDX-License-Identifier: GPL-2.0
2/* Copyright(c) 2019 Intel Corporation. All rights rsvd. */
3#include <linux/init.h>
4#include <linux/kernel.h>
5#include <linux/module.h>
6#include <linux/slab.h>
7#include <linux/pci.h>
8#include <linux/interrupt.h>
9#include <linux/delay.h>
10#include <linux/dma-mapping.h>
11#include <linux/workqueue.h>
12#include <linux/aer.h>
13#include <linux/fs.h>
14#include <linux/io-64-nonatomic-lo-hi.h>
15#include <linux/device.h>
16#include <linux/idr.h>
17#include <linux/iommu.h>
18#include <uapi/linux/idxd.h>
19#include <linux/dmaengine.h>
20#include "../dmaengine.h"

--- 79 unchanged lines hidden (view full) ---

100 dev_dbg(dev, "Requested idxd-misc handler on msix vector %d\n", ie->vector);
101
102 for (i = 0; i < idxd->max_wqs; i++) {
103 int msix_idx = i + 1;
104
105 ie = idxd_get_ie(idxd, msix_idx);
106 ie->id = msix_idx;
107 ie->int_handle = INVALID_INT_HANDLE;
12#include <linux/fs.h>
13#include <linux/io-64-nonatomic-lo-hi.h>
14#include <linux/device.h>
15#include <linux/idr.h>
16#include <linux/iommu.h>
17#include <uapi/linux/idxd.h>
18#include <linux/dmaengine.h>
19#include "../dmaengine.h"

--- 79 unchanged lines hidden (view full) ---

99 dev_dbg(dev, "Requested idxd-misc handler on msix vector %d\n", ie->vector);
100
101 for (i = 0; i < idxd->max_wqs; i++) {
102 int msix_idx = i + 1;
103
104 ie = idxd_get_ie(idxd, msix_idx);
105 ie->id = msix_idx;
106 ie->int_handle = INVALID_INT_HANDLE;
108 ie->pasid = IOMMU_PASID_INVALID;
107 ie->pasid = INVALID_IOASID;
109
110 spin_lock_init(&ie->list_lock);
111 init_llist_head(&ie->pending_llist);
112 INIT_LIST_HEAD(&ie->work_list);
113 }
114
115 idxd_unmask_error_interrupts(idxd);
116 return 0;

--- 267 unchanged lines hidden (view full) ---

384 idxd->wqcfg_offset = offsets.wqcfg * IDXD_TABLE_MULT;
385 dev_dbg(dev, "IDXD Work Queue Config Offset: %#x\n", idxd->wqcfg_offset);
386 idxd->msix_perm_offset = offsets.msix_perm * IDXD_TABLE_MULT;
387 dev_dbg(dev, "IDXD MSIX Permission Offset: %#x\n", idxd->msix_perm_offset);
388 idxd->perfmon_offset = offsets.perfmon * IDXD_TABLE_MULT;
389 dev_dbg(dev, "IDXD Perfmon Offset: %#x\n", idxd->perfmon_offset);
390}
391
108
109 spin_lock_init(&ie->list_lock);
110 init_llist_head(&ie->pending_llist);
111 INIT_LIST_HEAD(&ie->work_list);
112 }
113
114 idxd_unmask_error_interrupts(idxd);
115 return 0;

--- 267 unchanged lines hidden (view full) ---

383 idxd->wqcfg_offset = offsets.wqcfg * IDXD_TABLE_MULT;
384 dev_dbg(dev, "IDXD Work Queue Config Offset: %#x\n", idxd->wqcfg_offset);
385 idxd->msix_perm_offset = offsets.msix_perm * IDXD_TABLE_MULT;
386 dev_dbg(dev, "IDXD MSIX Permission Offset: %#x\n", idxd->msix_perm_offset);
387 idxd->perfmon_offset = offsets.perfmon * IDXD_TABLE_MULT;
388 dev_dbg(dev, "IDXD Perfmon Offset: %#x\n", idxd->perfmon_offset);
389}
390
392static void multi_u64_to_bmap(unsigned long *bmap, u64 *val, int count)
391void multi_u64_to_bmap(unsigned long *bmap, u64 *val, int count)
393{
394 int i, j, nr;
395
396 for (i = 0, nr = 0; i < count; i++) {
397 for (j = 0; j < BITS_PER_LONG_LONG; j++) {
398 if (val[i] & BIT(j))
399 set_bit(nr, bmap);
400 nr++;

--- 392 unchanged lines hidden --- 		392{
393 int i, j, nr;
394
395 for (i = 0, nr = 0; i < count; i++) {
396 for (j = 0; j < BITS_PER_LONG_LONG; j++) {
397 if (val[i] & BIT(j))
398 set_bit(nr, bmap);
399 nr++;

--- 392 unchanged lines hidden ---