device.c (2e21dee6a46a66e4c2ced778485e1044101edee4) device.c (d5638de827cff0fce77007e426ec0ffdedf68a44)
1// SPDX-License-Identifier: GPL-2.0
2/* Copyright(c) 2019 Intel Corporation. All rights rsvd. */
3#include <linux/init.h>
4#include <linux/kernel.h>
5#include <linux/module.h>
6#include <linux/pci.h>
7#include <linux/io-64-nonatomic-lo-hi.h>
8#include <linux/dmaengine.h>

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770 * at minimal page size aligned address. No manual alignment required.
771 */
772 addr = dma_alloc_coherent(dev, size, &dma_addr, GFP_KERNEL);
773 if (!addr) {
774 rc = -ENOMEM;
775 goto err_alloc;
776 }
777
1// SPDX-License-Identifier: GPL-2.0
2/* Copyright(c) 2019 Intel Corporation. All rights rsvd. */
3#include <linux/init.h>
4#include <linux/kernel.h>
5#include <linux/module.h>
6#include <linux/pci.h>
7#include <linux/io-64-nonatomic-lo-hi.h>
8#include <linux/dmaengine.h>

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770 * at minimal page size aligned address. No manual alignment required.
771 */
772 addr = dma_alloc_coherent(dev, size, &dma_addr, GFP_KERNEL);
773 if (!addr) {
774 rc = -ENOMEM;
775 goto err_alloc;
776 }
777
778 spin_lock(&evl->lock);
778 mutex_lock(&evl->lock);
779 evl->log = addr;
780 evl->dma = dma_addr;
781 evl->log_size = size;
782 evl->bmap = bmap;
783
784 memset(&evlcfg, 0, sizeof(evlcfg));
785 evlcfg.bits[0] = dma_addr & GENMASK(63, 12);
786 evlcfg.size = evl->size;

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791 genctrl.bits = ioread32(idxd->reg_base + IDXD_GENCTRL_OFFSET);
792 genctrl.evl_int_en = 1;
793 iowrite32(genctrl.bits, idxd->reg_base + IDXD_GENCTRL_OFFSET);
794
795 gencfg.bits = ioread32(idxd->reg_base + IDXD_GENCFG_OFFSET);
796 gencfg.evl_en = 1;
797 iowrite32(gencfg.bits, idxd->reg_base + IDXD_GENCFG_OFFSET);
798
779 evl->log = addr;
780 evl->dma = dma_addr;
781 evl->log_size = size;
782 evl->bmap = bmap;
783
784 memset(&evlcfg, 0, sizeof(evlcfg));
785 evlcfg.bits[0] = dma_addr & GENMASK(63, 12);
786 evlcfg.size = evl->size;

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791 genctrl.bits = ioread32(idxd->reg_base + IDXD_GENCTRL_OFFSET);
792 genctrl.evl_int_en = 1;
793 iowrite32(genctrl.bits, idxd->reg_base + IDXD_GENCTRL_OFFSET);
794
795 gencfg.bits = ioread32(idxd->reg_base + IDXD_GENCFG_OFFSET);
796 gencfg.evl_en = 1;
797 iowrite32(gencfg.bits, idxd->reg_base + IDXD_GENCFG_OFFSET);
798
799 spin_unlock(&evl->lock);
799 mutex_unlock(&evl->lock);
800 return 0;
801
802err_alloc:
803 bitmap_free(bmap);
804err_bmap:
805 return rc;
806}
807

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814 union genctrl_reg genctrl;
815 struct device *dev = &idxd->pdev->dev;
816 struct idxd_evl *evl = idxd->evl;
817
818 gencfg.bits = ioread32(idxd->reg_base + IDXD_GENCFG_OFFSET);
819 if (!gencfg.evl_en)
820 return;
821
800 return 0;
801
802err_alloc:
803 bitmap_free(bmap);
804err_bmap:
805 return rc;
806}
807

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814 union genctrl_reg genctrl;
815 struct device *dev = &idxd->pdev->dev;
816 struct idxd_evl *evl = idxd->evl;
817
818 gencfg.bits = ioread32(idxd->reg_base + IDXD_GENCFG_OFFSET);
819 if (!gencfg.evl_en)
820 return;
821
822 spin_lock(&evl->lock);
822 mutex_lock(&evl->lock);
823 gencfg.evl_en = 0;
824 iowrite32(gencfg.bits, idxd->reg_base + IDXD_GENCFG_OFFSET);
825
826 genctrl.bits = ioread32(idxd->reg_base + IDXD_GENCTRL_OFFSET);
827 genctrl.evl_int_en = 0;
828 iowrite32(genctrl.bits, idxd->reg_base + IDXD_GENCTRL_OFFSET);
829
830 iowrite64(0, idxd->reg_base + IDXD_EVLCFG_OFFSET);
831 iowrite64(0, idxd->reg_base + IDXD_EVLCFG_OFFSET + 8);
832
833 bitmap_free(evl->bmap);
834 evl_log = evl->log;
835 evl_log_size = evl->log_size;
836 evl_dma = evl->dma;
837 evl->log = NULL;
838 evl->size = IDXD_EVL_SIZE_MIN;
823 gencfg.evl_en = 0;
824 iowrite32(gencfg.bits, idxd->reg_base + IDXD_GENCFG_OFFSET);
825
826 genctrl.bits = ioread32(idxd->reg_base + IDXD_GENCTRL_OFFSET);
827 genctrl.evl_int_en = 0;
828 iowrite32(genctrl.bits, idxd->reg_base + IDXD_GENCTRL_OFFSET);
829
830 iowrite64(0, idxd->reg_base + IDXD_EVLCFG_OFFSET);
831 iowrite64(0, idxd->reg_base + IDXD_EVLCFG_OFFSET + 8);
832
833 bitmap_free(evl->bmap);
834 evl_log = evl->log;
835 evl_log_size = evl->log_size;
836 evl_dma = evl->dma;
837 evl->log = NULL;
838 evl->size = IDXD_EVL_SIZE_MIN;
839 spin_unlock(&evl->lock);
839 mutex_unlock(&evl->lock);
840
841 dma_free_coherent(dev, evl_log_size, evl_log, evl_dma);
842}
843
844static void idxd_group_config_write(struct idxd_group *group)
845{
846 struct idxd_device *idxd = group->idxd;
847 struct device *dev = &idxd->pdev->dev;

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841 dma_free_coherent(dev, evl_log_size, evl_log, evl_dma);
842}
843
844static void idxd_group_config_write(struct idxd_group *group)
845{
846 struct idxd_device *idxd = group->idxd;
847 struct device *dev = &idxd->pdev->dev;

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