core.c (2ac5e38ea4203852d6e99edd3cf11f044b0a409f) core.c (7b0c03ecc42fb223baf015877fee9d517c2c8af1)
1/*
2 * Core driver for the Synopsys DesignWare DMA Controller
3 *
4 * Copyright (C) 2007-2008 Atmel Corporation
5 * Copyright (C) 2010-2011 ST Microelectronics
6 * Copyright (C) 2013 Intel Corporation
7 *
8 * This program is free software; you can redistribute it and/or modify

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155 cfghi |= IDMA32C_CFGH_SRC_PER_EXT(dwc->dws.src_id >> 4 & 0x3);
156
157 channel_writel(dwc, CFG_LO, cfglo);
158 channel_writel(dwc, CFG_HI, cfghi);
159}
160
161static void dwc_initialize_chan_dw(struct dw_dma_chan *dwc)
162{
1/*
2 * Core driver for the Synopsys DesignWare DMA Controller
3 *
4 * Copyright (C) 2007-2008 Atmel Corporation
5 * Copyright (C) 2010-2011 ST Microelectronics
6 * Copyright (C) 2013 Intel Corporation
7 *
8 * This program is free software; you can redistribute it and/or modify

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155 cfghi |= IDMA32C_CFGH_SRC_PER_EXT(dwc->dws.src_id >> 4 & 0x3);
156
157 channel_writel(dwc, CFG_LO, cfglo);
158 channel_writel(dwc, CFG_HI, cfghi);
159}
160
161static void dwc_initialize_chan_dw(struct dw_dma_chan *dwc)
162{
163 struct dw_dma *dw = to_dw_dma(dwc->chan.device);
163 u32 cfghi = DWC_CFGH_FIFO_MODE;
164 u32 cfglo = DWC_CFGL_CH_PRIOR(dwc->priority);
165 bool hs_polarity = dwc->dws.hs_polarity;
166
167 cfghi |= DWC_CFGH_DST_PER(dwc->dws.dst_id);
168 cfghi |= DWC_CFGH_SRC_PER(dwc->dws.src_id);
164 u32 cfghi = DWC_CFGH_FIFO_MODE;
165 u32 cfglo = DWC_CFGL_CH_PRIOR(dwc->priority);
166 bool hs_polarity = dwc->dws.hs_polarity;
167
168 cfghi |= DWC_CFGH_DST_PER(dwc->dws.dst_id);
169 cfghi |= DWC_CFGH_SRC_PER(dwc->dws.src_id);
170 cfghi |= DWC_CFGH_PROTCTL(dw->pdata->protctl);
169
170 /* Set polarity of handshake interface */
171 cfglo |= hs_polarity ? DWC_CFGL_HS_DST_POL | DWC_CFGL_HS_SRC_POL : 0;
172
173 channel_writel(dwc, CFG_LO, cfglo);
174 channel_writel(dwc, CFG_HI, cfghi);
175}
176

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172 /* Set polarity of handshake interface */
173 cfglo |= hs_polarity ? DWC_CFGL_HS_DST_POL | DWC_CFGL_HS_SRC_POL : 0;
174
175 channel_writel(dwc, CFG_LO, cfglo);
176 channel_writel(dwc, CFG_HI, cfghi);
177}
178

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