| cxl.h (d17d0540a0dbf109210f7b57a37571e2978da0fa) | cxl.h (54cdbf845cf719c09b45ae588cba469aabb3159c) |
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| 1/* SPDX-License-Identifier: GPL-2.0-only */ 2/* Copyright(c) 2020 Intel Corporation. */ 3 4#ifndef __CXL_H__ 5#define __CXL_H__ 6 7#include <linux/libnvdimm.h> 8#include <linux/bitfield.h> --- 149 unchanged lines hidden (view full) --- 158 struct cxl_register_map *map); 159int cxl_map_device_regs(struct pci_dev *pdev, 160 struct cxl_device_regs *regs, 161 struct cxl_register_map *map); 162 163enum cxl_regloc_type; 164int cxl_find_regblock(struct pci_dev *pdev, enum cxl_regloc_type type, 165 struct cxl_register_map *map); | 1/* SPDX-License-Identifier: GPL-2.0-only */ 2/* Copyright(c) 2020 Intel Corporation. */ 3 4#ifndef __CXL_H__ 5#define __CXL_H__ 6 7#include <linux/libnvdimm.h> 8#include <linux/bitfield.h> --- 149 unchanged lines hidden (view full) --- 158 struct cxl_register_map *map); 159int cxl_map_device_regs(struct pci_dev *pdev, 160 struct cxl_device_regs *regs, 161 struct cxl_register_map *map); 162 163enum cxl_regloc_type; 164int cxl_find_regblock(struct pci_dev *pdev, enum cxl_regloc_type type, 165 struct cxl_register_map *map); |
| 166void __iomem *devm_cxl_iomap_block(struct device *dev, resource_size_t addr, 167 resource_size_t length); |
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| 166 167#define CXL_RESOURCE_NONE ((resource_size_t) -1) 168#define CXL_TARGET_STRLEN 20 169 170/* 171 * cxl_decoder flags that define the type of memory / devices this 172 * decoder supports as well as configuration lock status See "CXL 2.0 173 * 8.2.5.12.7 CXL HDM Decoder 0 Control Register" for details. --- 175 unchanged lines hidden (view full) --- 349#define cxl_driver_register(x) __cxl_driver_register(x, THIS_MODULE, KBUILD_MODNAME) 350void cxl_driver_unregister(struct cxl_driver *cxl_drv); 351 352#define module_cxl_driver(__cxl_driver) \ 353 module_driver(__cxl_driver, cxl_driver_register, cxl_driver_unregister) 354 355#define CXL_DEVICE_NVDIMM_BRIDGE 1 356#define CXL_DEVICE_NVDIMM 2 | 168 169#define CXL_RESOURCE_NONE ((resource_size_t) -1) 170#define CXL_TARGET_STRLEN 20 171 172/* 173 * cxl_decoder flags that define the type of memory / devices this 174 * decoder supports as well as configuration lock status See "CXL 2.0 175 * 8.2.5.12.7 CXL HDM Decoder 0 Control Register" for details. --- 175 unchanged lines hidden (view full) --- 351#define cxl_driver_register(x) __cxl_driver_register(x, THIS_MODULE, KBUILD_MODNAME) 352void cxl_driver_unregister(struct cxl_driver *cxl_drv); 353 354#define module_cxl_driver(__cxl_driver) \ 355 module_driver(__cxl_driver, cxl_driver_register, cxl_driver_unregister) 356 357#define CXL_DEVICE_NVDIMM_BRIDGE 1 358#define CXL_DEVICE_NVDIMM 2 |
| 359#define CXL_DEVICE_PORT 3 360#define CXL_DEVICE_ROOT 4 |
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| 357 358#define MODULE_ALIAS_CXL(type) MODULE_ALIAS("cxl:t" __stringify(type) "*") 359#define CXL_MODALIAS_FMT "cxl:t%d" 360 361struct cxl_nvdimm_bridge *to_cxl_nvdimm_bridge(struct device *dev); 362struct cxl_nvdimm_bridge *devm_cxl_add_nvdimm_bridge(struct device *host, 363 struct cxl_port *port); 364struct cxl_nvdimm *to_cxl_nvdimm(struct device *dev); --- 92 unchanged lines hidden --- | 361 362#define MODULE_ALIAS_CXL(type) MODULE_ALIAS("cxl:t" __stringify(type) "*") 363#define CXL_MODALIAS_FMT "cxl:t%d" 364 365struct cxl_nvdimm_bridge *to_cxl_nvdimm_bridge(struct device *dev); 366struct cxl_nvdimm_bridge *devm_cxl_add_nvdimm_bridge(struct device *host, 367 struct cxl_port *port); 368struct cxl_nvdimm *to_cxl_nvdimm(struct device *dev); --- 92 unchanged lines hidden --- |