| cxl.h (bd09626b39dff97779e1543e25e60ab2876e7e88) | cxl.h (2905cb5236cba63a5dc8a83752dcc31f3cc819f9) |
|---|---|
| 1/* SPDX-License-Identifier: GPL-2.0-only */ 2/* Copyright(c) 2020 Intel Corporation. */ 3 4#ifndef __CXL_H__ 5#define __CXL_H__ 6 7#include <linux/libnvdimm.h> 8#include <linux/bitfield.h> --- 118 unchanged lines hidden (view full) --- 127#define CXL_RAS_UNCORRECTABLE_MASK_MASK (GENMASK(16, 14) | GENMASK(11, 0)) 128#define CXL_RAS_UNCORRECTABLE_SEVERITY_OFFSET 0x8 129#define CXL_RAS_UNCORRECTABLE_SEVERITY_MASK (GENMASK(16, 14) | GENMASK(11, 0)) 130#define CXL_RAS_CORRECTABLE_STATUS_OFFSET 0xC 131#define CXL_RAS_CORRECTABLE_STATUS_MASK GENMASK(6, 0) 132#define CXL_RAS_CORRECTABLE_MASK_OFFSET 0x10 133#define CXL_RAS_CORRECTABLE_MASK_MASK GENMASK(6, 0) 134#define CXL_RAS_CAP_CONTROL_OFFSET 0x14 | 1/* SPDX-License-Identifier: GPL-2.0-only */ 2/* Copyright(c) 2020 Intel Corporation. */ 3 4#ifndef __CXL_H__ 5#define __CXL_H__ 6 7#include <linux/libnvdimm.h> 8#include <linux/bitfield.h> --- 118 unchanged lines hidden (view full) --- 127#define CXL_RAS_UNCORRECTABLE_MASK_MASK (GENMASK(16, 14) | GENMASK(11, 0)) 128#define CXL_RAS_UNCORRECTABLE_SEVERITY_OFFSET 0x8 129#define CXL_RAS_UNCORRECTABLE_SEVERITY_MASK (GENMASK(16, 14) | GENMASK(11, 0)) 130#define CXL_RAS_CORRECTABLE_STATUS_OFFSET 0xC 131#define CXL_RAS_CORRECTABLE_STATUS_MASK GENMASK(6, 0) 132#define CXL_RAS_CORRECTABLE_MASK_OFFSET 0x10 133#define CXL_RAS_CORRECTABLE_MASK_MASK GENMASK(6, 0) 134#define CXL_RAS_CAP_CONTROL_OFFSET 0x14 |
| 135#define CXL_RAS_CAP_CONTROL_FE_MASK GENMASK(5, 0) |
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| 135#define CXL_RAS_HEADER_LOG_OFFSET 0x18 136#define CXL_RAS_CAPABILITY_LENGTH 0x58 137 138/* CXL 2.0 8.2.8.1 Device Capabilities Array Register */ 139#define CXLDEV_CAP_ARRAY_OFFSET 0x0 140#define CXLDEV_CAP_ARRAY_CAP_ID 0 141#define CXLDEV_CAP_ARRAY_ID_MASK GENMASK_ULL(15, 0) 142#define CXLDEV_CAP_ARRAY_COUNT_MASK GENMASK_ULL(47, 32) --- 542 unchanged lines hidden --- | 136#define CXL_RAS_HEADER_LOG_OFFSET 0x18 137#define CXL_RAS_CAPABILITY_LENGTH 0x58 138 139/* CXL 2.0 8.2.8.1 Device Capabilities Array Register */ 140#define CXLDEV_CAP_ARRAY_OFFSET 0x0 141#define CXLDEV_CAP_ARRAY_CAP_ID 0 142#define CXLDEV_CAP_ARRAY_ID_MASK GENMASK_ULL(15, 0) 143#define CXLDEV_CAP_ARRAY_COUNT_MASK GENMASK_ULL(47, 32) --- 542 unchanged lines hidden --- |