| cxl.h (0d8eae7b124e2ddaee00f186fe922450faad0ed7) | cxl.h (4a20bc3e207488064e08fc5d7220d6acf95c80dd) |
|---|---|
| 1/* SPDX-License-Identifier: GPL-2.0-only */ 2/* Copyright(c) 2020 Intel Corporation. */ 3 4#ifndef __CXL_H__ 5#define __CXL_H__ 6 7#include <linux/libnvdimm.h> 8#include <linux/bitfield.h> --- 126 unchanged lines hidden (view full) --- 135#define CXL_RAS_CORRECTABLE_STATUS_OFFSET 0xC 136#define CXL_RAS_CORRECTABLE_STATUS_MASK GENMASK(6, 0) 137#define CXL_RAS_CORRECTABLE_MASK_OFFSET 0x10 138#define CXL_RAS_CORRECTABLE_MASK_MASK GENMASK(6, 0) 139#define CXL_RAS_CAP_CONTROL_OFFSET 0x14 140#define CXL_RAS_CAP_CONTROL_FE_MASK GENMASK(5, 0) 141#define CXL_RAS_HEADER_LOG_OFFSET 0x18 142#define CXL_RAS_CAPABILITY_LENGTH 0x58 | 1/* SPDX-License-Identifier: GPL-2.0-only */ 2/* Copyright(c) 2020 Intel Corporation. */ 3 4#ifndef __CXL_H__ 5#define __CXL_H__ 6 7#include <linux/libnvdimm.h> 8#include <linux/bitfield.h> --- 126 unchanged lines hidden (view full) --- 135#define CXL_RAS_CORRECTABLE_STATUS_OFFSET 0xC 136#define CXL_RAS_CORRECTABLE_STATUS_MASK GENMASK(6, 0) 137#define CXL_RAS_CORRECTABLE_MASK_OFFSET 0x10 138#define CXL_RAS_CORRECTABLE_MASK_MASK GENMASK(6, 0) 139#define CXL_RAS_CAP_CONTROL_OFFSET 0x14 140#define CXL_RAS_CAP_CONTROL_FE_MASK GENMASK(5, 0) 141#define CXL_RAS_HEADER_LOG_OFFSET 0x18 142#define CXL_RAS_CAPABILITY_LENGTH 0x58 |
| 143#define CXL_HEADERLOG_SIZE SZ_512 144#define CXL_HEADERLOG_SIZE_U32 SZ_512 / sizeof(u32) |
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| 143 144/* CXL 2.0 8.2.8.1 Device Capabilities Array Register */ 145#define CXLDEV_CAP_ARRAY_OFFSET 0x0 146#define CXLDEV_CAP_ARRAY_CAP_ID 0 147#define CXLDEV_CAP_ARRAY_ID_MASK GENMASK_ULL(15, 0) 148#define CXLDEV_CAP_ARRAY_COUNT_MASK GENMASK_ULL(47, 32) 149/* CXL 2.0 8.2.8.2 CXL Device Capability Header Register */ 150#define CXLDEV_CAP_HDR_CAP_ID_MASK GENMASK(15, 0) --- 555 unchanged lines hidden --- | 145 146/* CXL 2.0 8.2.8.1 Device Capabilities Array Register */ 147#define CXLDEV_CAP_ARRAY_OFFSET 0x0 148#define CXLDEV_CAP_ARRAY_CAP_ID 0 149#define CXLDEV_CAP_ARRAY_ID_MASK GENMASK_ULL(15, 0) 150#define CXLDEV_CAP_ARRAY_COUNT_MASK GENMASK_ULL(47, 32) 151/* CXL 2.0 8.2.8.2 CXL Device Capability Header Register */ 152#define CXLDEV_CAP_HDR_CAP_ID_MASK GENMASK(15, 0) --- 555 unchanged lines hidden --- |