cxl.h (08422378c4adacf528d573bb1631d4818f8f9a01) cxl.h (4812be97c015bddf12c70155858df43acc35a4eb)
1/* SPDX-License-Identifier: GPL-2.0-only */
2/* Copyright(c) 2020 Intel Corporation. */
3
4#ifndef __CXL_H__
5#define __CXL_H__
6
7#include <linux/bitfield.h>
8#include <linux/bitops.h>
9#include <linux/io.h>
10
1/* SPDX-License-Identifier: GPL-2.0-only */
2/* Copyright(c) 2020 Intel Corporation. */
3
4#ifndef __CXL_H__
5#define __CXL_H__
6
7#include <linux/bitfield.h>
8#include <linux/bitops.h>
9#include <linux/io.h>
10
11/**
12 * DOC: cxl objects
13 *
14 * The CXL core objects like ports, decoders, and regions are shared
15 * between the subsystem drivers cxl_acpi, cxl_pci, and core drivers
16 * (port-driver, region-driver, nvdimm object-drivers... etc).
17 */
18
11/* CXL 2.0 8.2.5 CXL.cache and CXL.mem Registers*/
12#define CXL_CM_OFFSET 0x1000
13#define CXL_CM_CAP_HDR_OFFSET 0x0
14#define CXL_CM_CAP_HDR_ID_MASK GENMASK(15, 0)
15#define CM_CAP_HDR_CAP_ID 1
16#define CXL_CM_CAP_HDR_VERSION_MASK GENMASK(19, 16)
17#define CM_CAP_HDR_CAP_VERSION 1
18#define CXL_CM_CAP_HDR_CACHE_MEM_VERSION_MASK GENMASK(23, 20)

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140 struct cxl_device_reg_map *map);
141int cxl_map_component_regs(struct pci_dev *pdev,
142 struct cxl_component_regs *regs,
143 struct cxl_register_map *map);
144int cxl_map_device_regs(struct pci_dev *pdev,
145 struct cxl_device_regs *regs,
146 struct cxl_register_map *map);
147
19/* CXL 2.0 8.2.5 CXL.cache and CXL.mem Registers*/
20#define CXL_CM_OFFSET 0x1000
21#define CXL_CM_CAP_HDR_OFFSET 0x0
22#define CXL_CM_CAP_HDR_ID_MASK GENMASK(15, 0)
23#define CM_CAP_HDR_CAP_ID 1
24#define CXL_CM_CAP_HDR_VERSION_MASK GENMASK(19, 16)
25#define CM_CAP_HDR_CAP_VERSION 1
26#define CXL_CM_CAP_HDR_CACHE_MEM_VERSION_MASK GENMASK(23, 20)

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148 struct cxl_device_reg_map *map);
149int cxl_map_component_regs(struct pci_dev *pdev,
150 struct cxl_component_regs *regs,
151 struct cxl_register_map *map);
152int cxl_map_device_regs(struct pci_dev *pdev,
153 struct cxl_device_regs *regs,
154 struct cxl_register_map *map);
155
156#define CXL_RESOURCE_NONE ((resource_size_t) -1)
157
158/**
159 * struct cxl_port - logical collection of upstream port devices and
160 * downstream port devices to construct a CXL memory
161 * decode hierarchy.
162 * @dev: this port's device
163 * @uport: PCI or platform device implementing the upstream port capability
164 * @id: id for port device-name
165 * @component_reg_phys: component register capability base address (optional)
166 */
167struct cxl_port {
168 struct device dev;
169 struct device *uport;
170 int id;
171 resource_size_t component_reg_phys;
172};
173
174struct cxl_port *to_cxl_port(struct device *dev);
175struct cxl_port *devm_cxl_add_port(struct device *host, struct device *uport,
176 resource_size_t component_reg_phys,
177 struct cxl_port *parent_port);
178
148extern struct bus_type cxl_bus_type;
149#endif /* __CXL_H__ */
179extern struct bus_type cxl_bus_type;
180#endif /* __CXL_H__ */