| trace.h (71919308943d2574717517e3698e655ef0fc6f1c) | trace.h (2c92ca849fcc6ee7d0c358e9959abc9f58661aea) |
|---|---|
| 1// SPDX-License-Identifier: GPL-2.0 2/* Copyright(c) 2022 Intel Corporation. All rights reserved. */ 3#undef TRACE_SYSTEM 4#define TRACE_SYSTEM cxl 5 6#if !defined(_CXL_EVENTS_H) || defined(TRACE_HEADER_MULTI_READ) 7#define _CXL_EVENTS_H 8 --- 46 unchanged lines hidden (view full) --- 55 __string(memdev, dev_name(&cxlmd->dev)) 56 __string(host, dev_name(cxlmd->dev.parent)) 57 __field(u64, serial) 58 __field(u32, status) 59 __field(u32, first_error) 60 __array(u32, header_log, CXL_HEADERLOG_SIZE_U32) 61 ), 62 TP_fast_assign( | 1// SPDX-License-Identifier: GPL-2.0 2/* Copyright(c) 2022 Intel Corporation. All rights reserved. */ 3#undef TRACE_SYSTEM 4#define TRACE_SYSTEM cxl 5 6#if !defined(_CXL_EVENTS_H) || defined(TRACE_HEADER_MULTI_READ) 7#define _CXL_EVENTS_H 8 --- 46 unchanged lines hidden (view full) --- 55 __string(memdev, dev_name(&cxlmd->dev)) 56 __string(host, dev_name(cxlmd->dev.parent)) 57 __field(u64, serial) 58 __field(u32, status) 59 __field(u32, first_error) 60 __array(u32, header_log, CXL_HEADERLOG_SIZE_U32) 61 ), 62 TP_fast_assign( |
| 63 __assign_str(memdev, dev_name(&cxlmd->dev)); 64 __assign_str(host, dev_name(cxlmd->dev.parent)); | 63 __assign_str(memdev); 64 __assign_str(host); |
| 65 __entry->serial = cxlmd->cxlds->serial; 66 __entry->status = status; 67 __entry->first_error = fe; 68 /* 69 * Embed the 512B headerlog data for user app retrieval and 70 * parsing, but no need to print this in the trace buffer. 71 */ 72 memcpy(__entry->header_log, hl, CXL_HEADERLOG_SIZE); --- 28 unchanged lines hidden (view full) --- 101 TP_ARGS(cxlmd, status), 102 TP_STRUCT__entry( 103 __string(memdev, dev_name(&cxlmd->dev)) 104 __string(host, dev_name(cxlmd->dev.parent)) 105 __field(u64, serial) 106 __field(u32, status) 107 ), 108 TP_fast_assign( | 65 __entry->serial = cxlmd->cxlds->serial; 66 __entry->status = status; 67 __entry->first_error = fe; 68 /* 69 * Embed the 512B headerlog data for user app retrieval and 70 * parsing, but no need to print this in the trace buffer. 71 */ 72 memcpy(__entry->header_log, hl, CXL_HEADERLOG_SIZE); --- 28 unchanged lines hidden (view full) --- 101 TP_ARGS(cxlmd, status), 102 TP_STRUCT__entry( 103 __string(memdev, dev_name(&cxlmd->dev)) 104 __string(host, dev_name(cxlmd->dev.parent)) 105 __field(u64, serial) 106 __field(u32, status) 107 ), 108 TP_fast_assign( |
| 109 __assign_str(memdev, dev_name(&cxlmd->dev)); 110 __assign_str(host, dev_name(cxlmd->dev.parent)); | 109 __assign_str(memdev); 110 __assign_str(host); |
| 111 __entry->serial = cxlmd->cxlds->serial; 112 __entry->status = status; 113 ), 114 TP_printk("memdev=%s host=%s serial=%lld: status: '%s'", 115 __get_str(memdev), __get_str(host), __entry->serial, 116 show_ce_errs(__entry->status) 117 ) 118); --- 18 unchanged lines hidden (view full) --- 137 __field(int, log) 138 __field(u64, serial) 139 __field(u64, first_ts) 140 __field(u64, last_ts) 141 __field(u16, count) 142 ), 143 144 TP_fast_assign( | 111 __entry->serial = cxlmd->cxlds->serial; 112 __entry->status = status; 113 ), 114 TP_printk("memdev=%s host=%s serial=%lld: status: '%s'", 115 __get_str(memdev), __get_str(host), __entry->serial, 116 show_ce_errs(__entry->status) 117 ) 118); --- 18 unchanged lines hidden (view full) --- 137 __field(int, log) 138 __field(u64, serial) 139 __field(u64, first_ts) 140 __field(u64, last_ts) 141 __field(u16, count) 142 ), 143 144 TP_fast_assign( |
| 145 __assign_str(memdev, dev_name(&cxlmd->dev)); 146 __assign_str(host, dev_name(cxlmd->dev.parent)); | 145 __assign_str(memdev); 146 __assign_str(host); |
| 147 __entry->serial = cxlmd->cxlds->serial; 148 __entry->log = log; 149 __entry->count = le16_to_cpu(payload->overflow_err_count); 150 __entry->first_ts = le64_to_cpu(payload->first_overflow_timestamp); 151 __entry->last_ts = le64_to_cpu(payload->last_overflow_timestamp); 152 ), 153 154 TP_printk("memdev=%s host=%s serial=%lld: log=%s : %u records from %llu to %llu", --- 40 unchanged lines hidden (view full) --- 195 __field(u32, hdr_flags) \ 196 __field(u16, hdr_handle) \ 197 __field(u16, hdr_related_handle) \ 198 __field(u64, hdr_timestamp) \ 199 __field(u8, hdr_length) \ 200 __field(u8, hdr_maint_op_class) 201 202#define CXL_EVT_TP_fast_assign(cxlmd, l, hdr) \ | 147 __entry->serial = cxlmd->cxlds->serial; 148 __entry->log = log; 149 __entry->count = le16_to_cpu(payload->overflow_err_count); 150 __entry->first_ts = le64_to_cpu(payload->first_overflow_timestamp); 151 __entry->last_ts = le64_to_cpu(payload->last_overflow_timestamp); 152 ), 153 154 TP_printk("memdev=%s host=%s serial=%lld: log=%s : %u records from %llu to %llu", --- 40 unchanged lines hidden (view full) --- 195 __field(u32, hdr_flags) \ 196 __field(u16, hdr_handle) \ 197 __field(u16, hdr_related_handle) \ 198 __field(u64, hdr_timestamp) \ 199 __field(u8, hdr_length) \ 200 __field(u8, hdr_maint_op_class) 201 202#define CXL_EVT_TP_fast_assign(cxlmd, l, hdr) \ |
| 203 __assign_str(memdev, dev_name(&(cxlmd)->dev)); \ 204 __assign_str(host, dev_name((cxlmd)->dev.parent)); \ | 203 __assign_str(memdev); \ 204 __assign_str(host); \ |
| 205 __entry->log = (l); \ 206 __entry->serial = (cxlmd)->cxlds->serial; \ 207 __entry->hdr_length = (hdr).length; \ 208 __entry->hdr_flags = get_unaligned_le24((hdr).flags); \ 209 __entry->hdr_handle = le16_to_cpu((hdr).handle); \ 210 __entry->hdr_related_handle = le16_to_cpu((hdr).related_handle); \ 211 __entry->hdr_timestamp = le64_to_cpu((hdr).timestamp); \ 212 __entry->hdr_maint_op_class = (hdr).maint_op_class --- 35 unchanged lines hidden (view full) --- 248 * Physical Address field masks 249 * 250 * General Media Event Record 251 * CXL rev 3.0 Section 8.2.9.2.1.1; Table 8-43 252 * 253 * DRAM Event Record 254 * CXL rev 3.0 section 8.2.9.2.1.2; Table 8-44 255 */ | 205 __entry->log = (l); \ 206 __entry->serial = (cxlmd)->cxlds->serial; \ 207 __entry->hdr_length = (hdr).length; \ 208 __entry->hdr_flags = get_unaligned_le24((hdr).flags); \ 209 __entry->hdr_handle = le16_to_cpu((hdr).handle); \ 210 __entry->hdr_related_handle = le16_to_cpu((hdr).related_handle); \ 211 __entry->hdr_timestamp = le64_to_cpu((hdr).timestamp); \ 212 __entry->hdr_maint_op_class = (hdr).maint_op_class --- 35 unchanged lines hidden (view full) --- 248 * Physical Address field masks 249 * 250 * General Media Event Record 251 * CXL rev 3.0 Section 8.2.9.2.1.1; Table 8-43 252 * 253 * DRAM Event Record 254 * CXL rev 3.0 section 8.2.9.2.1.2; Table 8-44 255 */ |
| 256#define CXL_DPA_FLAGS_MASK 0x3F 257#define CXL_DPA_MASK (~CXL_DPA_FLAGS_MASK) | 256#define CXL_DPA_FLAGS_MASK GENMASK(1, 0) 257#define CXL_DPA_MASK GENMASK_ULL(63, 6) |
| 258 259#define CXL_DPA_VOLATILE BIT(0) 260#define CXL_DPA_NOT_REPAIRABLE BIT(1) 261#define show_dpa_flags(flags) __print_flags(flags, "|", \ 262 { CXL_DPA_VOLATILE, "VOLATILE" }, \ 263 { CXL_DPA_NOT_REPAIRABLE, "NOT_REPAIRABLE" } \ 264) 265 --- 45 unchanged lines hidden (view full) --- 311 { CXL_GMER_VALID_RANK, "RANK" }, \ 312 { CXL_GMER_VALID_DEVICE, "DEVICE" }, \ 313 { CXL_GMER_VALID_COMPONENT, "COMPONENT" } \ 314) 315 316TRACE_EVENT(cxl_general_media, 317 318 TP_PROTO(const struct cxl_memdev *cxlmd, enum cxl_event_log_type log, | 258 259#define CXL_DPA_VOLATILE BIT(0) 260#define CXL_DPA_NOT_REPAIRABLE BIT(1) 261#define show_dpa_flags(flags) __print_flags(flags, "|", \ 262 { CXL_DPA_VOLATILE, "VOLATILE" }, \ 263 { CXL_DPA_NOT_REPAIRABLE, "NOT_REPAIRABLE" } \ 264) 265 --- 45 unchanged lines hidden (view full) --- 311 { CXL_GMER_VALID_RANK, "RANK" }, \ 312 { CXL_GMER_VALID_DEVICE, "DEVICE" }, \ 313 { CXL_GMER_VALID_COMPONENT, "COMPONENT" } \ 314) 315 316TRACE_EVENT(cxl_general_media, 317 318 TP_PROTO(const struct cxl_memdev *cxlmd, enum cxl_event_log_type log, |
| 319 struct cxl_event_gen_media *rec), | 319 struct cxl_region *cxlr, u64 hpa, struct cxl_event_gen_media *rec), |
| 320 | 320 |
| 321 TP_ARGS(cxlmd, log, rec), | 321 TP_ARGS(cxlmd, log, cxlr, hpa, rec), |
| 322 323 TP_STRUCT__entry( 324 CXL_EVT_TP_entry 325 /* General Media */ 326 __field(u64, dpa) 327 __field(u8, descriptor) 328 __field(u8, type) 329 __field(u8, transaction_type) 330 __field(u8, channel) 331 __field(u32, device) 332 __array(u8, comp_id, CXL_EVENT_GEN_MED_COMP_ID_SIZE) | 322 323 TP_STRUCT__entry( 324 CXL_EVT_TP_entry 325 /* General Media */ 326 __field(u64, dpa) 327 __field(u8, descriptor) 328 __field(u8, type) 329 __field(u8, transaction_type) 330 __field(u8, channel) 331 __field(u32, device) 332 __array(u8, comp_id, CXL_EVENT_GEN_MED_COMP_ID_SIZE) |
| 333 __field(u16, validity_flags) | |
| 334 /* Following are out of order to pack trace record */ | 333 /* Following are out of order to pack trace record */ |
| 334 __field(u64, hpa) 335 __field_struct(uuid_t, region_uuid) 336 __field(u16, validity_flags) |
|
| 335 __field(u8, rank) 336 __field(u8, dpa_flags) | 337 __field(u8, rank) 338 __field(u8, dpa_flags) |
| 339 __string(region_name, cxlr ? dev_name(&cxlr->dev) : "") |
|
| 337 ), 338 339 TP_fast_assign( 340 CXL_EVT_TP_fast_assign(cxlmd, log, rec->hdr); 341 __entry->hdr_uuid = CXL_EVENT_GEN_MEDIA_UUID; 342 343 /* General Media */ 344 __entry->dpa = le64_to_cpu(rec->phys_addr); --- 4 unchanged lines hidden (view full) --- 349 __entry->type = rec->type; 350 __entry->transaction_type = rec->transaction_type; 351 __entry->channel = rec->channel; 352 __entry->rank = rec->rank; 353 __entry->device = get_unaligned_le24(rec->device); 354 memcpy(__entry->comp_id, &rec->component_id, 355 CXL_EVENT_GEN_MED_COMP_ID_SIZE); 356 __entry->validity_flags = get_unaligned_le16(&rec->validity_flags); | 340 ), 341 342 TP_fast_assign( 343 CXL_EVT_TP_fast_assign(cxlmd, log, rec->hdr); 344 __entry->hdr_uuid = CXL_EVENT_GEN_MEDIA_UUID; 345 346 /* General Media */ 347 __entry->dpa = le64_to_cpu(rec->phys_addr); --- 4 unchanged lines hidden (view full) --- 352 __entry->type = rec->type; 353 __entry->transaction_type = rec->transaction_type; 354 __entry->channel = rec->channel; 355 __entry->rank = rec->rank; 356 __entry->device = get_unaligned_le24(rec->device); 357 memcpy(__entry->comp_id, &rec->component_id, 358 CXL_EVENT_GEN_MED_COMP_ID_SIZE); 359 __entry->validity_flags = get_unaligned_le16(&rec->validity_flags); |
| 360 __entry->hpa = hpa; 361 if (cxlr) { 362 __assign_str(region_name); 363 uuid_copy(&__entry->region_uuid, &cxlr->params.uuid); 364 } else { 365 __assign_str(region_name); 366 uuid_copy(&__entry->region_uuid, &uuid_null); 367 } |
|
| 357 ), 358 359 CXL_EVT_TP_printk("dpa=%llx dpa_flags='%s' " \ 360 "descriptor='%s' type='%s' transaction_type='%s' channel=%u rank=%u " \ | 368 ), 369 370 CXL_EVT_TP_printk("dpa=%llx dpa_flags='%s' " \ 371 "descriptor='%s' type='%s' transaction_type='%s' channel=%u rank=%u " \ |
| 361 "device=%x comp_id=%s validity_flags='%s'", | 372 "device=%x comp_id=%s validity_flags='%s' " \ 373 "hpa=%llx region=%s region_uuid=%pUb", |
| 362 __entry->dpa, show_dpa_flags(__entry->dpa_flags), 363 show_event_desc_flags(__entry->descriptor), 364 show_mem_event_type(__entry->type), 365 show_trans_type(__entry->transaction_type), 366 __entry->channel, __entry->rank, __entry->device, 367 __print_hex(__entry->comp_id, CXL_EVENT_GEN_MED_COMP_ID_SIZE), | 374 __entry->dpa, show_dpa_flags(__entry->dpa_flags), 375 show_event_desc_flags(__entry->descriptor), 376 show_mem_event_type(__entry->type), 377 show_trans_type(__entry->transaction_type), 378 __entry->channel, __entry->rank, __entry->device, 379 __print_hex(__entry->comp_id, CXL_EVENT_GEN_MED_COMP_ID_SIZE), |
| 368 show_valid_flags(__entry->validity_flags) | 380 show_valid_flags(__entry->validity_flags), 381 __entry->hpa, __get_str(region_name), &__entry->region_uuid |
| 369 ) 370); 371 372/* 373 * DRAM Event Record - DER 374 * 375 * CXL rev 3.0 section 8.2.9.2.1.2; Table 8-44 376 */ --- 18 unchanged lines hidden (view full) --- 395 { CXL_DER_VALID_ROW, "ROW" }, \ 396 { CXL_DER_VALID_COLUMN, "COLUMN" }, \ 397 { CXL_DER_VALID_CORRECTION_MASK, "CORRECTION MASK" } \ 398) 399 400TRACE_EVENT(cxl_dram, 401 402 TP_PROTO(const struct cxl_memdev *cxlmd, enum cxl_event_log_type log, | 382 ) 383); 384 385/* 386 * DRAM Event Record - DER 387 * 388 * CXL rev 3.0 section 8.2.9.2.1.2; Table 8-44 389 */ --- 18 unchanged lines hidden (view full) --- 408 { CXL_DER_VALID_ROW, "ROW" }, \ 409 { CXL_DER_VALID_COLUMN, "COLUMN" }, \ 410 { CXL_DER_VALID_CORRECTION_MASK, "CORRECTION MASK" } \ 411) 412 413TRACE_EVENT(cxl_dram, 414 415 TP_PROTO(const struct cxl_memdev *cxlmd, enum cxl_event_log_type log, |
| 403 struct cxl_event_dram *rec), | 416 struct cxl_region *cxlr, u64 hpa, struct cxl_event_dram *rec), |
| 404 | 417 |
| 405 TP_ARGS(cxlmd, log, rec), | 418 TP_ARGS(cxlmd, log, cxlr, hpa, rec), |
| 406 407 TP_STRUCT__entry( 408 CXL_EVT_TP_entry 409 /* DRAM */ 410 __field(u64, dpa) 411 __field(u8, descriptor) 412 __field(u8, type) 413 __field(u8, transaction_type) 414 __field(u8, channel) 415 __field(u16, validity_flags) 416 __field(u16, column) /* Out of order to pack trace record */ 417 __field(u32, nibble_mask) 418 __field(u32, row) 419 __array(u8, cor_mask, CXL_EVENT_DER_CORRECTION_MASK_SIZE) | 419 420 TP_STRUCT__entry( 421 CXL_EVT_TP_entry 422 /* DRAM */ 423 __field(u64, dpa) 424 __field(u8, descriptor) 425 __field(u8, type) 426 __field(u8, transaction_type) 427 __field(u8, channel) 428 __field(u16, validity_flags) 429 __field(u16, column) /* Out of order to pack trace record */ 430 __field(u32, nibble_mask) 431 __field(u32, row) 432 __array(u8, cor_mask, CXL_EVENT_DER_CORRECTION_MASK_SIZE) |
| 433 __field(u64, hpa) 434 __field_struct(uuid_t, region_uuid) |
|
| 420 __field(u8, rank) /* Out of order to pack trace record */ 421 __field(u8, bank_group) /* Out of order to pack trace record */ 422 __field(u8, bank) /* Out of order to pack trace record */ 423 __field(u8, dpa_flags) /* Out of order to pack trace record */ | 435 __field(u8, rank) /* Out of order to pack trace record */ 436 __field(u8, bank_group) /* Out of order to pack trace record */ 437 __field(u8, bank) /* Out of order to pack trace record */ 438 __field(u8, dpa_flags) /* Out of order to pack trace record */ |
| 439 __string(region_name, cxlr ? dev_name(&cxlr->dev) : "") |
|
| 424 ), 425 426 TP_fast_assign( 427 CXL_EVT_TP_fast_assign(cxlmd, log, rec->hdr); 428 __entry->hdr_uuid = CXL_EVENT_DRAM_UUID; 429 430 /* DRAM */ 431 __entry->dpa = le64_to_cpu(rec->phys_addr); --- 7 unchanged lines hidden (view full) --- 439 __entry->rank = rec->rank; 440 __entry->nibble_mask = get_unaligned_le24(rec->nibble_mask); 441 __entry->bank_group = rec->bank_group; 442 __entry->bank = rec->bank; 443 __entry->row = get_unaligned_le24(rec->row); 444 __entry->column = get_unaligned_le16(rec->column); 445 memcpy(__entry->cor_mask, &rec->correction_mask, 446 CXL_EVENT_DER_CORRECTION_MASK_SIZE); | 440 ), 441 442 TP_fast_assign( 443 CXL_EVT_TP_fast_assign(cxlmd, log, rec->hdr); 444 __entry->hdr_uuid = CXL_EVENT_DRAM_UUID; 445 446 /* DRAM */ 447 __entry->dpa = le64_to_cpu(rec->phys_addr); --- 7 unchanged lines hidden (view full) --- 455 __entry->rank = rec->rank; 456 __entry->nibble_mask = get_unaligned_le24(rec->nibble_mask); 457 __entry->bank_group = rec->bank_group; 458 __entry->bank = rec->bank; 459 __entry->row = get_unaligned_le24(rec->row); 460 __entry->column = get_unaligned_le16(rec->column); 461 memcpy(__entry->cor_mask, &rec->correction_mask, 462 CXL_EVENT_DER_CORRECTION_MASK_SIZE); |
| 463 __entry->hpa = hpa; 464 if (cxlr) { 465 __assign_str(region_name); 466 uuid_copy(&__entry->region_uuid, &cxlr->params.uuid); 467 } else { 468 __assign_str(region_name); 469 uuid_copy(&__entry->region_uuid, &uuid_null); 470 } |
|
| 447 ), 448 449 CXL_EVT_TP_printk("dpa=%llx dpa_flags='%s' descriptor='%s' type='%s' " \ 450 "transaction_type='%s' channel=%u rank=%u nibble_mask=%x " \ 451 "bank_group=%u bank=%u row=%u column=%u cor_mask=%s " \ | 471 ), 472 473 CXL_EVT_TP_printk("dpa=%llx dpa_flags='%s' descriptor='%s' type='%s' " \ 474 "transaction_type='%s' channel=%u rank=%u nibble_mask=%x " \ 475 "bank_group=%u bank=%u row=%u column=%u cor_mask=%s " \ |
| 452 "validity_flags='%s'", | 476 "validity_flags='%s' " \ 477 "hpa=%llx region=%s region_uuid=%pUb", |
| 453 __entry->dpa, show_dpa_flags(__entry->dpa_flags), 454 show_event_desc_flags(__entry->descriptor), 455 show_mem_event_type(__entry->type), 456 show_trans_type(__entry->transaction_type), 457 __entry->channel, __entry->rank, __entry->nibble_mask, 458 __entry->bank_group, __entry->bank, 459 __entry->row, __entry->column, 460 __print_hex(__entry->cor_mask, CXL_EVENT_DER_CORRECTION_MASK_SIZE), | 478 __entry->dpa, show_dpa_flags(__entry->dpa_flags), 479 show_event_desc_flags(__entry->descriptor), 480 show_mem_event_type(__entry->type), 481 show_trans_type(__entry->transaction_type), 482 __entry->channel, __entry->rank, __entry->nibble_mask, 483 __entry->bank_group, __entry->bank, 484 __entry->row, __entry->column, 485 __print_hex(__entry->cor_mask, CXL_EVENT_DER_CORRECTION_MASK_SIZE), |
| 461 show_dram_valid_flags(__entry->validity_flags) | 486 show_dram_valid_flags(__entry->validity_flags), 487 __entry->hpa, __get_str(region_name), &__entry->region_uuid |
| 462 ) 463); 464 465/* 466 * Memory Module Event Record - MMER 467 * 468 * CXL res 3.0 section 8.2.9.2.1.3; Table 8-45 469 */ --- 167 unchanged lines hidden (view full) --- 637 (__cxl_poison_addr(record) & CXL_POISON_START_MASK) 638#define cxl_poison_record_source(record) \ 639 (__cxl_poison_addr(record) & CXL_POISON_SOURCE_MASK) 640#define cxl_poison_record_dpa_length(record) \ 641 (le32_to_cpu(record->length) * CXL_POISON_LEN_MULT) 642#define cxl_poison_overflow(flags, time) \ 643 (flags & CXL_POISON_FLAG_OVERFLOW ? le64_to_cpu(time) : 0) 644 | 488 ) 489); 490 491/* 492 * Memory Module Event Record - MMER 493 * 494 * CXL res 3.0 section 8.2.9.2.1.3; Table 8-45 495 */ --- 167 unchanged lines hidden (view full) --- 663 (__cxl_poison_addr(record) & CXL_POISON_START_MASK) 664#define cxl_poison_record_source(record) \ 665 (__cxl_poison_addr(record) & CXL_POISON_SOURCE_MASK) 666#define cxl_poison_record_dpa_length(record) \ 667 (le32_to_cpu(record->length) * CXL_POISON_LEN_MULT) 668#define cxl_poison_overflow(flags, time) \ 669 (flags & CXL_POISON_FLAG_OVERFLOW ? le64_to_cpu(time) : 0) 670 |
| 645u64 cxl_trace_hpa(struct cxl_region *cxlr, struct cxl_memdev *memdev, u64 dpa); 646 | |
| 647TRACE_EVENT(cxl_poison, 648 649 TP_PROTO(struct cxl_memdev *cxlmd, struct cxl_region *cxlr, 650 const struct cxl_poison_record *record, u8 flags, 651 __le64 overflow_ts, enum cxl_poison_trace_type trace_type), 652 653 TP_ARGS(cxlmd, cxlr, record, flags, overflow_ts, trace_type), 654 --- 8 unchanged lines hidden (view full) --- 663 __field(u64, dpa) 664 __field(u32, dpa_length) 665 __array(char, uuid, 16) 666 __field(u8, source) 667 __field(u8, flags) 668 ), 669 670 TP_fast_assign( | 671TRACE_EVENT(cxl_poison, 672 673 TP_PROTO(struct cxl_memdev *cxlmd, struct cxl_region *cxlr, 674 const struct cxl_poison_record *record, u8 flags, 675 __le64 overflow_ts, enum cxl_poison_trace_type trace_type), 676 677 TP_ARGS(cxlmd, cxlr, record, flags, overflow_ts, trace_type), 678 --- 8 unchanged lines hidden (view full) --- 687 __field(u64, dpa) 688 __field(u32, dpa_length) 689 __array(char, uuid, 16) 690 __field(u8, source) 691 __field(u8, flags) 692 ), 693 694 TP_fast_assign( |
| 671 __assign_str(memdev, dev_name(&cxlmd->dev)); 672 __assign_str(host, dev_name(cxlmd->dev.parent)); | 695 __assign_str(memdev); 696 __assign_str(host); |
| 673 __entry->serial = cxlmd->cxlds->serial; 674 __entry->overflow_ts = cxl_poison_overflow(flags, overflow_ts); 675 __entry->dpa = cxl_poison_record_dpa(record); 676 __entry->dpa_length = cxl_poison_record_dpa_length(record); 677 __entry->source = cxl_poison_record_source(record); 678 __entry->trace_type = trace_type; 679 __entry->flags = flags; 680 if (cxlr) { | 697 __entry->serial = cxlmd->cxlds->serial; 698 __entry->overflow_ts = cxl_poison_overflow(flags, overflow_ts); 699 __entry->dpa = cxl_poison_record_dpa(record); 700 __entry->dpa_length = cxl_poison_record_dpa_length(record); 701 __entry->source = cxl_poison_record_source(record); 702 __entry->trace_type = trace_type; 703 __entry->flags = flags; 704 if (cxlr) { |
| 681 __assign_str(region, dev_name(&cxlr->dev)); | 705 __assign_str(region); |
| 682 memcpy(__entry->uuid, &cxlr->params.uuid, 16); 683 __entry->hpa = cxl_trace_hpa(cxlr, cxlmd, 684 __entry->dpa); 685 } else { | 706 memcpy(__entry->uuid, &cxlr->params.uuid, 16); 707 __entry->hpa = cxl_trace_hpa(cxlr, cxlmd, 708 __entry->dpa); 709 } else { |
| 686 __assign_str(region, ""); | 710 __assign_str(region); |
| 687 memset(__entry->uuid, 0, 16); 688 __entry->hpa = ULLONG_MAX; 689 } 690 ), 691 692 TP_printk("memdev=%s host=%s serial=%lld trace_type=%s region=%s " \ 693 "region_uuid=%pU hpa=0x%llx dpa=0x%llx dpa_length=0x%x " \ 694 "source=%s flags=%s overflow_time=%llu", --- 19 unchanged lines hidden --- | 711 memset(__entry->uuid, 0, 16); 712 __entry->hpa = ULLONG_MAX; 713 } 714 ), 715 716 TP_printk("memdev=%s host=%s serial=%lld trace_type=%s region=%s " \ 717 "region_uuid=%pU hpa=0x%llx dpa=0x%llx dpa_length=0x%x " \ 718 "source=%s flags=%s overflow_time=%llu", --- 19 unchanged lines hidden --- |