acpi.c (d17d0540a0dbf109210f7b57a37571e2978da0fa) acpi.c (54cdbf845cf719c09b45ae588cba469aabb3159c)
1// SPDX-License-Identifier: GPL-2.0-only
2/* Copyright(c) 2021 Intel Corporation. All rights reserved. */
3#include <linux/platform_device.h>
4#include <linux/module.h>
5#include <linux/device.h>
6#include <linux/kernel.h>
7#include <linux/acpi.h>
8#include <linux/pci.h>

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164 */
165static int add_host_bridge_uport(struct device *match, void *arg)
166{
167 struct cxl_port *root_port = arg;
168 struct device *host = root_port->dev.parent;
169 struct acpi_device *bridge = to_cxl_host_bridge(host, match);
170 struct acpi_pci_root *pci_root;
171 struct cxl_dport *dport;
1// SPDX-License-Identifier: GPL-2.0-only
2/* Copyright(c) 2021 Intel Corporation. All rights reserved. */
3#include <linux/platform_device.h>
4#include <linux/module.h>
5#include <linux/device.h>
6#include <linux/kernel.h>
7#include <linux/acpi.h>
8#include <linux/pci.h>

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164 */
165static int add_host_bridge_uport(struct device *match, void *arg)
166{
167 struct cxl_port *root_port = arg;
168 struct device *host = root_port->dev.parent;
169 struct acpi_device *bridge = to_cxl_host_bridge(host, match);
170 struct acpi_pci_root *pci_root;
171 struct cxl_dport *dport;
172 struct cxl_hdm *cxlhdm;
173 struct cxl_port *port;
174 int rc;
175
176 if (!bridge)
177 return 0;
178
179 dport = find_dport_by_dev(root_port, match);
180 if (!dport) {

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192 return rc;
193
194 port = devm_cxl_add_port(host, match, dport->component_reg_phys,
195 root_port);
196 if (IS_ERR(port))
197 return PTR_ERR(port);
198 dev_dbg(host, "%s: add: %s\n", dev_name(match), dev_name(&port->dev));
199
172 struct cxl_port *port;
173 int rc;
174
175 if (!bridge)
176 return 0;
177
178 dport = find_dport_by_dev(root_port, match);
179 if (!dport) {

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191 return rc;
192
193 port = devm_cxl_add_port(host, match, dport->component_reg_phys,
194 root_port);
195 if (IS_ERR(port))
196 return PTR_ERR(port);
197 dev_dbg(host, "%s: add: %s\n", dev_name(match), dev_name(&port->dev));
198
200 rc = devm_cxl_port_enumerate_dports(host, port);
201 if (rc < 0)
202 return rc;
203 cxl_device_lock(&port->dev);
204 if (rc == 1) {
205 rc = devm_cxl_add_passthrough_decoder(host, port);
206 goto out;
207 }
208
209 cxlhdm = devm_cxl_setup_hdm(host, port);
210 if (IS_ERR(cxlhdm)) {
211 rc = PTR_ERR(cxlhdm);
212 goto out;
213 }
214
215 rc = devm_cxl_enumerate_decoders(host, cxlhdm);
216 if (rc)
217 dev_err(&port->dev, "Couldn't enumerate decoders (%d)\n", rc);
218
219out:
220 cxl_device_unlock(&port->dev);
221 return rc;
199 return 0;
222}
223
224struct cxl_chbs_context {
225 struct device *dev;
226 unsigned long long uid;
227 resource_size_t chbcr;
228};
229

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273 acpi_table_parse_cedt(ACPI_CEDT_TYPE_CHBS, cxl_get_chbcr, &ctx);
274
275 if (ctx.chbcr == 0) {
276 dev_warn(host, "No CHBS found for Host Bridge: %s\n",
277 dev_name(match));
278 return 0;
279 }
280
200}
201
202struct cxl_chbs_context {
203 struct device *dev;
204 unsigned long long uid;
205 resource_size_t chbcr;
206};
207

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251 acpi_table_parse_cedt(ACPI_CEDT_TYPE_CHBS, cxl_get_chbcr, &ctx);
252
253 if (ctx.chbcr == 0) {
254 dev_warn(host, "No CHBS found for Host Bridge: %s\n",
255 dev_name(match));
256 return 0;
257 }
258
281 cxl_device_lock(&root_port->dev);
282 dport = devm_cxl_add_dport(host, root_port, match, uid, ctx.chbcr);
259 dport = devm_cxl_add_dport(host, root_port, match, uid, ctx.chbcr);
283 cxl_device_unlock(&root_port->dev);
284 if (IS_ERR(dport)) {
285 dev_err(host, "failed to add downstream port: %s\n",
286 dev_name(match));
287 return PTR_ERR(dport);
288 }
289 dev_dbg(host, "add dport%llu: %s\n", uid, dev_name(match));
290 return 0;
291}

--- 85 unchanged lines hidden --- 		260 if (IS_ERR(dport)) {
261 dev_err(host, "failed to add downstream port: %s\n",
262 dev_name(match));
263 return PTR_ERR(dport);
264 }
265 dev_dbg(host, "add dport%llu: %s\n", uid, dev_name(match));
266 return 0;
267}

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