| Kconfig (a1c613ae4c322ddd58d5a8539dbfba2a0380a8c0) | Kconfig (ad6f04c0269b0b7908f09621d3b3c90def39a297) |
|---|---|
| 1# SPDX-License-Identifier: GPL-2.0-only 2menuconfig CXL_BUS 3 tristate "CXL (Compute Express Link) Devices Support" 4 depends on PCI 5 select FW_LOADER 6 select FW_UPLOAD 7 select PCI_DOE | 1# SPDX-License-Identifier: GPL-2.0-only 2menuconfig CXL_BUS 3 tristate "CXL (Compute Express Link) Devices Support" 4 depends on PCI 5 select FW_LOADER 6 select FW_UPLOAD 7 select PCI_DOE |
| 8 select FIRMWARE_TABLE |
|
| 8 help 9 CXL is a bus that is electrically compatible with PCI Express, but 10 layers three protocols on that signalling (CXL.io, CXL.cache, and 11 CXL.mem). The CXL.cache protocol allows devices to hold cachelines 12 locally, the CXL.mem protocol allows devices to be fully coherent 13 memory targets, the CXL.io protocol is equivalent to PCI Express. 14 Say 'y' to enable support for the configuration and management of 15 devices supporting these protocols. --- 33 unchanged lines hidden (view full) --- 49 the hardware, even commands that may crash the kernel due to their 50 potential impact to memory currently in use by the kernel. 51 52 If developing CXL hardware or the driver say Y, otherwise say N. 53 54config CXL_ACPI 55 tristate "CXL ACPI: Platform Support" 56 depends on ACPI | 9 help 10 CXL is a bus that is electrically compatible with PCI Express, but 11 layers three protocols on that signalling (CXL.io, CXL.cache, and 12 CXL.mem). The CXL.cache protocol allows devices to hold cachelines 13 locally, the CXL.mem protocol allows devices to be fully coherent 14 memory targets, the CXL.io protocol is equivalent to PCI Express. 15 Say 'y' to enable support for the configuration and management of 16 devices supporting these protocols. --- 33 unchanged lines hidden (view full) --- 50 the hardware, even commands that may crash the kernel due to their 51 potential impact to memory currently in use by the kernel. 52 53 If developing CXL hardware or the driver say Y, otherwise say N. 54 55config CXL_ACPI 56 tristate "CXL ACPI: Platform Support" 57 depends on ACPI |
| 58 depends on ACPI_NUMA |
|
| 57 default CXL_BUS 58 select ACPI_TABLE_LIB | 59 default CXL_BUS 60 select ACPI_TABLE_LIB |
| 61 select ACPI_HMAT |
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| 59 help 60 Enable support for host managed device memory (HDM) resources 61 published by a platform's ACPI CXL memory layout description. See 62 Chapter 9.14.1 CXL Early Discovery Table (CEDT) in the CXL 2.0 63 specification, and CXL Fixed Memory Window Structures (CEDT.CFMWS) 64 (https://www.computeexpresslink.org/spec-landing). The CXL core 65 consumes these resource to publish the root of a cxl_port decode 66 hierarchy to map regions that represent System RAM, or Persistent --- 91 unchanged lines hidden --- | 62 help 63 Enable support for host managed device memory (HDM) resources 64 published by a platform's ACPI CXL memory layout description. See 65 Chapter 9.14.1 CXL Early Discovery Table (CEDT) in the CXL 2.0 66 specification, and CXL Fixed Memory Window Structures (CEDT.CFMWS) 67 (https://www.computeexpresslink.org/spec-landing). The CXL core 68 consumes these resource to publish the root of a cxl_port decode 69 hierarchy to map regions that represent System RAM, or Persistent --- 91 unchanged lines hidden --- |