| Kconfig (71af75b6929458d85f63c0649dc26d6f4c19729e) | Kconfig (f4ce1f766f1ebf39161b3b9447a83f4f1dfe593b) |
|---|---|
| 1# SPDX-License-Identifier: GPL-2.0-only 2menuconfig CXL_BUS 3 tristate "CXL (Compute Express Link) Devices Support" 4 depends on PCI 5 help 6 CXL is a bus that is electrically compatible with PCI Express, but 7 layers three protocols on that signalling (CXL.io, CXL.cache, and 8 CXL.mem). The CXL.cache protocol allows devices to hold cachelines --- 37 unchanged lines hidden (view full) --- 46 potential impact to memory currently in use by the kernel. 47 48 If developing CXL hardware or the driver say Y, otherwise say N. 49 50config CXL_ACPI 51 tristate "CXL ACPI: Platform Support" 52 depends on ACPI 53 default CXL_BUS | 1# SPDX-License-Identifier: GPL-2.0-only 2menuconfig CXL_BUS 3 tristate "CXL (Compute Express Link) Devices Support" 4 depends on PCI 5 help 6 CXL is a bus that is electrically compatible with PCI Express, but 7 layers three protocols on that signalling (CXL.io, CXL.cache, and 8 CXL.mem). The CXL.cache protocol allows devices to hold cachelines --- 37 unchanged lines hidden (view full) --- 46 potential impact to memory currently in use by the kernel. 47 48 If developing CXL hardware or the driver say Y, otherwise say N. 49 50config CXL_ACPI 51 tristate "CXL ACPI: Platform Support" 52 depends on ACPI 53 default CXL_BUS |
| 54 select ACPI_TABLE_LIB |
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| 54 help 55 Enable support for host managed device memory (HDM) resources 56 published by a platform's ACPI CXL memory layout description. See 57 Chapter 9.14.1 CXL Early Discovery Table (CEDT) in the CXL 2.0 58 specification, and CXL Fixed Memory Window Structures (CEDT.CFMWS) 59 (https://www.computeexpresslink.org/spec-landing). The CXL core 60 consumes these resource to publish the root of a cxl_port decode 61 hierarchy to map regions that represent System RAM, or Persistent --- 17 unchanged lines hidden --- | 55 help 56 Enable support for host managed device memory (HDM) resources 57 published by a platform's ACPI CXL memory layout description. See 58 Chapter 9.14.1 CXL Early Discovery Table (CEDT) in the CXL 2.0 59 specification, and CXL Fixed Memory Window Structures (CEDT.CFMWS) 60 (https://www.computeexpresslink.org/spec-landing). The CXL core 61 consumes these resource to publish the root of a cxl_port decode 62 hierarchy to map regions that represent System RAM, or Persistent --- 17 unchanged lines hidden --- |