talitos.c (5b859b6ebb18b37244d44b5300bf765694b7303c) talitos.c (ad42d5fc85383278663ecb58a24f6547ad0ba735)
1/*
2 * talitos - Freescale Integrated Security Engine (SEC) device driver
3 *
4 * Copyright (c) 2008-2011 Freescale Semiconductor, Inc.
5 *
6 * Scatterlist Crypto API glue code copied from files with the following:
7 * Copyright (c) 2006-2007 Herbert Xu <herbert@gondor.apana.org.au>
8 *

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94 dma_addr_t dma_desc;
95 void (*callback) (struct device *dev, struct talitos_desc *desc,
96 void *context, int error);
97 void *context;
98};
99
100/* per-channel fifo management */
101struct talitos_channel {
1/*
2 * talitos - Freescale Integrated Security Engine (SEC) device driver
3 *
4 * Copyright (c) 2008-2011 Freescale Semiconductor, Inc.
5 *
6 * Scatterlist Crypto API glue code copied from files with the following:
7 * Copyright (c) 2006-2007 Herbert Xu <herbert@gondor.apana.org.au>
8 *

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94 dma_addr_t dma_desc;
95 void (*callback) (struct device *dev, struct talitos_desc *desc,
96 void *context, int error);
97 void *context;
98};
99
100/* per-channel fifo management */
101struct talitos_channel {
102 void __iomem *reg;
103
102 /* request fifo */
103 struct talitos_request *fifo;
104
105 /* number of requests pending in channel h/w fifo */
106 atomic_t submit_count ____cacheline_aligned;
107
108 /* request submission (head) lock */
109 spinlock_t head_lock ____cacheline_aligned;

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192 be16_to_cpu(talitos_ptr->len), dir);
193}
194
195static int reset_channel(struct device *dev, int ch)
196{
197 struct talitos_private *priv = dev_get_drvdata(dev);
198 unsigned int timeout = TALITOS_TIMEOUT;
199
104 /* request fifo */
105 struct talitos_request *fifo;
106
107 /* number of requests pending in channel h/w fifo */
108 atomic_t submit_count ____cacheline_aligned;
109
110 /* request submission (head) lock */
111 spinlock_t head_lock ____cacheline_aligned;

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194 be16_to_cpu(talitos_ptr->len), dir);
195}
196
197static int reset_channel(struct device *dev, int ch)
198{
199 struct talitos_private *priv = dev_get_drvdata(dev);
200 unsigned int timeout = TALITOS_TIMEOUT;
201
200 setbits32(priv->reg + TALITOS_CCCR(ch), TALITOS_CCCR_RESET);
202 setbits32(priv->chan[ch].reg + TALITOS_CCCR, TALITOS_CCCR_RESET);
201
203
202 while ((in_be32(priv->reg + TALITOS_CCCR(ch)) & TALITOS_CCCR_RESET)
204 while ((in_be32(priv->chan[ch].reg + TALITOS_CCCR) & TALITOS_CCCR_RESET)
203 && --timeout)
204 cpu_relax();
205
206 if (timeout == 0) {
207 dev_err(dev, "failed to reset channel %d\n", ch);
208 return -EIO;
209 }
210
211 /* set 36-bit addressing, done writeback enable and done IRQ enable */
205 && --timeout)
206 cpu_relax();
207
208 if (timeout == 0) {
209 dev_err(dev, "failed to reset channel %d\n", ch);
210 return -EIO;
211 }
212
213 /* set 36-bit addressing, done writeback enable and done IRQ enable */
212 setbits32(priv->reg + TALITOS_CCCR_LO(ch), TALITOS_CCCR_LO_EAE |
214 setbits32(priv->chan[ch].reg + TALITOS_CCCR_LO, TALITOS_CCCR_LO_EAE |
213 TALITOS_CCCR_LO_CDWE | TALITOS_CCCR_LO_CDIE);
214
215 /* and ICCR writeback, if available */
216 if (priv->features & TALITOS_FTR_HW_AUTH_CHECK)
215 TALITOS_CCCR_LO_CDWE | TALITOS_CCCR_LO_CDIE);
216
217 /* and ICCR writeback, if available */
218 if (priv->features & TALITOS_FTR_HW_AUTH_CHECK)
217 setbits32(priv->reg + TALITOS_CCCR_LO(ch),
219 setbits32(priv->chan[ch].reg + TALITOS_CCCR_LO,
218 TALITOS_CCCR_LO_IWSE);
219
220 return 0;
221}
222
223static int reset_device(struct device *dev)
224{
225 struct talitos_private *priv = dev_get_drvdata(dev);

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323 /* increment fifo head */
324 priv->chan[ch].head = (priv->chan[ch].head + 1) & (priv->fifo_len - 1);
325
326 smp_wmb();
327 request->desc = desc;
328
329 /* GO! */
330 wmb();
220 TALITOS_CCCR_LO_IWSE);
221
222 return 0;
223}
224
225static int reset_device(struct device *dev)
226{
227 struct talitos_private *priv = dev_get_drvdata(dev);

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325 /* increment fifo head */
326 priv->chan[ch].head = (priv->chan[ch].head + 1) & (priv->fifo_len - 1);
327
328 smp_wmb();
329 request->desc = desc;
330
331 /* GO! */
332 wmb();
331 out_be32(priv->reg + TALITOS_FF(ch), upper_32_bits(request->dma_desc));
332 out_be32(priv->reg + TALITOS_FF_LO(ch),
333 out_be32(priv->chan[ch].reg + TALITOS_FF,
334 upper_32_bits(request->dma_desc));
335 out_be32(priv->chan[ch].reg + TALITOS_FF_LO,
333 lower_32_bits(request->dma_desc));
334
335 spin_unlock_irqrestore(&priv->chan[ch].head_lock, flags);
336
337 return -EINPROGRESS;
338}
339
340/*

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418 * locate current (offending) descriptor
419 */
420static u32 current_desc_hdr(struct device *dev, int ch)
421{
422 struct talitos_private *priv = dev_get_drvdata(dev);
423 int tail = priv->chan[ch].tail;
424 dma_addr_t cur_desc;
425
336 lower_32_bits(request->dma_desc));
337
338 spin_unlock_irqrestore(&priv->chan[ch].head_lock, flags);
339
340 return -EINPROGRESS;
341}
342
343/*

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421 * locate current (offending) descriptor
422 */
423static u32 current_desc_hdr(struct device *dev, int ch)
424{
425 struct talitos_private *priv = dev_get_drvdata(dev);
426 int tail = priv->chan[ch].tail;
427 dma_addr_t cur_desc;
428
426 cur_desc = in_be32(priv->reg + TALITOS_CDPR_LO(ch));
429 cur_desc = in_be32(priv->chan[ch].reg + TALITOS_CDPR_LO);
427
428 while (priv->chan[ch].fifo[tail].dma_desc != cur_desc) {
429 tail = (tail + 1) & (priv->fifo_len - 1);
430 if (tail == priv->chan[ch].tail) {
431 dev_err(dev, "couldn't locate current descriptor\n");
432 return 0;
433 }
434 }

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440 * user diagnostics; report root cause of error based on execution unit status
441 */
442static void report_eu_error(struct device *dev, int ch, u32 desc_hdr)
443{
444 struct talitos_private *priv = dev_get_drvdata(dev);
445 int i;
446
447 if (!desc_hdr)
430
431 while (priv->chan[ch].fifo[tail].dma_desc != cur_desc) {
432 tail = (tail + 1) & (priv->fifo_len - 1);
433 if (tail == priv->chan[ch].tail) {
434 dev_err(dev, "couldn't locate current descriptor\n");
435 return 0;
436 }
437 }

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443 * user diagnostics; report root cause of error based on execution unit status
444 */
445static void report_eu_error(struct device *dev, int ch, u32 desc_hdr)
446{
447 struct talitos_private *priv = dev_get_drvdata(dev);
448 int i;
449
450 if (!desc_hdr)
448 desc_hdr = in_be32(priv->reg + TALITOS_DESCBUF(ch));
451 desc_hdr = in_be32(priv->chan[ch].reg + TALITOS_DESCBUF);
449
450 switch (desc_hdr & DESC_HDR_SEL0_MASK) {
451 case DESC_HDR_SEL0_AFEU:
452 dev_err(dev, "AFEUISR 0x%08x_%08x\n",
453 in_be32(priv->reg + TALITOS_AFEUISR),
454 in_be32(priv->reg + TALITOS_AFEUISR_LO));
455 break;
456 case DESC_HDR_SEL0_DEU:

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502 dev_err(dev, "CRCUISR 0x%08x_%08x\n",
503 in_be32(priv->reg + TALITOS_CRCUISR),
504 in_be32(priv->reg + TALITOS_CRCUISR_LO));
505 break;
506 }
507
508 for (i = 0; i < 8; i++)
509 dev_err(dev, "DESCBUF 0x%08x_%08x\n",
452
453 switch (desc_hdr & DESC_HDR_SEL0_MASK) {
454 case DESC_HDR_SEL0_AFEU:
455 dev_err(dev, "AFEUISR 0x%08x_%08x\n",
456 in_be32(priv->reg + TALITOS_AFEUISR),
457 in_be32(priv->reg + TALITOS_AFEUISR_LO));
458 break;
459 case DESC_HDR_SEL0_DEU:

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505 dev_err(dev, "CRCUISR 0x%08x_%08x\n",
506 in_be32(priv->reg + TALITOS_CRCUISR),
507 in_be32(priv->reg + TALITOS_CRCUISR_LO));
508 break;
509 }
510
511 for (i = 0; i < 8; i++)
512 dev_err(dev, "DESCBUF 0x%08x_%08x\n",
510 in_be32(priv->reg + TALITOS_DESCBUF(ch) + 8*i),
511 in_be32(priv->reg + TALITOS_DESCBUF_LO(ch) + 8*i));
513 in_be32(priv->chan[ch].reg + TALITOS_DESCBUF + 8*i),
514 in_be32(priv->chan[ch].reg + TALITOS_DESCBUF_LO + 8*i));
512}
513
514/*
515 * recover from error interrupts
516 */
517static void talitos_error(unsigned long data, u32 isr, u32 isr_lo)
518{
519 struct device *dev = (struct device *)data;

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524
525 for (ch = 0; ch < priv->num_channels; ch++) {
526 /* skip channels without errors */
527 if (!(isr & (1 << (ch * 2 + 1))))
528 continue;
529
530 error = -EINVAL;
531
515}
516
517/*
518 * recover from error interrupts
519 */
520static void talitos_error(unsigned long data, u32 isr, u32 isr_lo)
521{
522 struct device *dev = (struct device *)data;

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527
528 for (ch = 0; ch < priv->num_channels; ch++) {
529 /* skip channels without errors */
530 if (!(isr & (1 << (ch * 2 + 1))))
531 continue;
532
533 error = -EINVAL;
534
532 v = in_be32(priv->reg + TALITOS_CCPSR(ch));
533 v_lo = in_be32(priv->reg + TALITOS_CCPSR_LO(ch));
535 v = in_be32(priv->chan[ch].reg + TALITOS_CCPSR);
536 v_lo = in_be32(priv->chan[ch].reg + TALITOS_CCPSR_LO);
534
535 if (v_lo & TALITOS_CCPSR_LO_DOF) {
536 dev_err(dev, "double fetch fifo overflow error\n");
537 error = -EAGAIN;
538 reset_ch = 1;
539 }
540 if (v_lo & TALITOS_CCPSR_LO_SOF) {
541 /* h/w dropped descriptor */

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563 if (v_lo & TALITOS_CCPSR_LO_SRL)
564 dev_err(dev, "scatter return/length error\n");
565
566 flush_channel(dev, ch, error, reset_ch);
567
568 if (reset_ch) {
569 reset_channel(dev, ch);
570 } else {
537
538 if (v_lo & TALITOS_CCPSR_LO_DOF) {
539 dev_err(dev, "double fetch fifo overflow error\n");
540 error = -EAGAIN;
541 reset_ch = 1;
542 }
543 if (v_lo & TALITOS_CCPSR_LO_SOF) {
544 /* h/w dropped descriptor */

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566 if (v_lo & TALITOS_CCPSR_LO_SRL)
567 dev_err(dev, "scatter return/length error\n");
568
569 flush_channel(dev, ch, error, reset_ch);
570
571 if (reset_ch) {
572 reset_channel(dev, ch);
573 } else {
571 setbits32(priv->reg + TALITOS_CCCR(ch),
574 setbits32(priv->chan[ch].reg + TALITOS_CCCR,
572 TALITOS_CCCR_CONT);
575 TALITOS_CCCR_CONT);
573 setbits32(priv->reg + TALITOS_CCCR_LO(ch), 0);
574 while ((in_be32(priv->reg + TALITOS_CCCR(ch)) &
576 setbits32(priv->chan[ch].reg + TALITOS_CCCR_LO, 0);
577 while ((in_be32(priv->chan[ch].reg + TALITOS_CCCR) &
575 TALITOS_CCCR_CONT) && --timeout)
576 cpu_relax();
577 if (timeout == 0) {
578 dev_err(dev, "failed to restart channel %d\n",
579 ch);
580 reset_dev = 1;
581 }
582 }

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2705 priv->chan = kzalloc(sizeof(struct talitos_channel) *
2706 priv->num_channels, GFP_KERNEL);
2707 if (!priv->chan) {
2708 dev_err(dev, "failed to allocate channel management space\n");
2709 err = -ENOMEM;
2710 goto err_out;
2711 }
2712
578 TALITOS_CCCR_CONT) && --timeout)
579 cpu_relax();
580 if (timeout == 0) {
581 dev_err(dev, "failed to restart channel %d\n",
582 ch);
583 reset_dev = 1;
584 }
585 }

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2708 priv->chan = kzalloc(sizeof(struct talitos_channel) *
2709 priv->num_channels, GFP_KERNEL);
2710 if (!priv->chan) {
2711 dev_err(dev, "failed to allocate channel management space\n");
2712 err = -ENOMEM;
2713 goto err_out;
2714 }
2715
2716 for (i = 0; i < priv->num_channels; i++)
2717 priv->chan[i].reg = priv->reg + TALITOS_CH_BASE_OFFSET +
2718 TALITOS_CH_STRIDE * (i + 1);
2719
2713 for (i = 0; i < priv->num_channels; i++) {
2714 spin_lock_init(&priv->chan[i].head_lock);
2715 spin_lock_init(&priv->chan[i].tail_lock);
2716 }
2717
2718 priv->fifo_len = roundup_pow_of_two(priv->chfifo_len);
2719
2720 for (i = 0; i < priv->num_channels; i++) {

--- 115 unchanged lines hidden --- 		2720 for (i = 0; i < priv->num_channels; i++) {
2721 spin_lock_init(&priv->chan[i].head_lock);
2722 spin_lock_init(&priv->chan[i].tail_lock);
2723 }
2724
2725 priv->fifo_len = roundup_pow_of_two(priv->chfifo_len);
2726
2727 for (i = 0; i < priv->num_channels; i++) {

--- 115 unchanged lines hidden ---