common.c (023265ed75d8792ca1d555430a8985511d3f8788) common.c (59e056cda4beb5412e3653e6360c2eb0fa770baa)
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (c) 2012-2014, The Linux Foundation. All rights reserved.
4 */
5
6#include <linux/err.h>
7#include <linux/interrupt.h>
8#include <linux/types.h>

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40qce_clear_array(struct qce_device *qce, u32 offset, unsigned int len)
41{
42 int i;
43
44 for (i = 0; i < len; i++)
45 qce_write(qce, offset + i * sizeof(u32), 0);
46}
47
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (c) 2012-2014, The Linux Foundation. All rights reserved.
4 */
5
6#include <linux/err.h>
7#include <linux/interrupt.h>
8#include <linux/types.h>

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40qce_clear_array(struct qce_device *qce, u32 offset, unsigned int len)
41{
42 int i;
43
44 for (i = 0; i < len; i++)
45 qce_write(qce, offset + i * sizeof(u32), 0);
46}
47
48static u32 qce_encr_cfg(unsigned long flags, u32 aes_key_size)
48static u32 qce_config_reg(struct qce_device *qce, int little)
49{
49{
50 u32 cfg = 0;
50 u32 beats = (qce->burst_size >> 3) - 1;
51 u32 pipe_pair = qce->pipe_pair_id;
52 u32 config;
51
53
52 if (IS_AES(flags)) {
53 if (aes_key_size == AES_KEYSIZE_128)
54 cfg |= ENCR_KEY_SZ_AES128 << ENCR_KEY_SZ_SHIFT;
55 else if (aes_key_size == AES_KEYSIZE_256)
56 cfg |= ENCR_KEY_SZ_AES256 << ENCR_KEY_SZ_SHIFT;
57 }
54 config = (beats << REQ_SIZE_SHIFT) & REQ_SIZE_MASK;
55 config |= BIT(MASK_DOUT_INTR_SHIFT) | BIT(MASK_DIN_INTR_SHIFT) |
56 BIT(MASK_OP_DONE_INTR_SHIFT) | BIT(MASK_ERR_INTR_SHIFT);
57 config |= (pipe_pair << PIPE_SET_SELECT_SHIFT) & PIPE_SET_SELECT_MASK;
58 config &= ~HIGH_SPD_EN_N_SHIFT;
58
59
59 if (IS_AES(flags))
60 cfg |= ENCR_ALG_AES << ENCR_ALG_SHIFT;
61 else if (IS_DES(flags) || IS_3DES(flags))
62 cfg |= ENCR_ALG_DES << ENCR_ALG_SHIFT;
60 if (little)
61 config |= BIT(LITTLE_ENDIAN_MODE_SHIFT);
63
62
64 if (IS_DES(flags))
65 cfg |= ENCR_KEY_SZ_DES << ENCR_KEY_SZ_SHIFT;
63 return config;
64}
66
65
67 if (IS_3DES(flags))
68 cfg |= ENCR_KEY_SZ_3DES << ENCR_KEY_SZ_SHIFT;
66void qce_cpu_to_be32p_array(__be32 *dst, const u8 *src, unsigned int len)
67{
68 __be32 *d = dst;
69 const u8 *s = src;
70 unsigned int n;
69
71
70 switch (flags & QCE_MODE_MASK) {
71 case QCE_MODE_ECB:
72 cfg |= ENCR_MODE_ECB << ENCR_MODE_SHIFT;
73 break;
74 case QCE_MODE_CBC:
75 cfg |= ENCR_MODE_CBC << ENCR_MODE_SHIFT;
76 break;
77 case QCE_MODE_CTR:
78 cfg |= ENCR_MODE_CTR << ENCR_MODE_SHIFT;
79 break;
80 case QCE_MODE_XTS:
81 cfg |= ENCR_MODE_XTS << ENCR_MODE_SHIFT;
82 break;
83 case QCE_MODE_CCM:
84 cfg |= ENCR_MODE_CCM << ENCR_MODE_SHIFT;
85 cfg |= LAST_CCM_XFR << LAST_CCM_SHIFT;
86 break;
87 default:
88 return ~0;
72 n = len / sizeof(u32);
73 for (; n > 0; n--) {
74 *d = cpu_to_be32p((const __u32 *) s);
75 s += sizeof(__u32);
76 d++;
89 }
77 }
78}
90
79
91 return cfg;
80static void qce_setup_config(struct qce_device *qce)
81{
82 u32 config;
83
84 /* get big endianness */
85 config = qce_config_reg(qce, 0);
86
87 /* clear status */
88 qce_write(qce, REG_STATUS, 0);
89 qce_write(qce, REG_CONFIG, config);
92}
93
90}
91
92static inline void qce_crypto_go(struct qce_device *qce)
93{
94 qce_write(qce, REG_GOPROC, BIT(GO_SHIFT) | BIT(RESULTS_DUMP_SHIFT));
95}
96
97#ifdef CONFIG_CRYPTO_DEV_QCE_SHA
94static u32 qce_auth_cfg(unsigned long flags, u32 key_size)
95{
96 u32 cfg = 0;
97
98 if (IS_AES(flags) && (IS_CCM(flags) || IS_CMAC(flags)))
99 cfg |= AUTH_ALG_AES << AUTH_ALG_SHIFT;
100 else
101 cfg |= AUTH_ALG_SHA << AUTH_ALG_SHIFT;

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132
133 if (IS_CBC(flags) || IS_CTR(flags) || IS_CCM(flags) ||
134 IS_CMAC(flags))
135 cfg |= BIT(AUTH_LAST_SHIFT) | BIT(AUTH_FIRST_SHIFT);
136
137 return cfg;
138}
139
98static u32 qce_auth_cfg(unsigned long flags, u32 key_size)
99{
100 u32 cfg = 0;
101
102 if (IS_AES(flags) && (IS_CCM(flags) || IS_CMAC(flags)))
103 cfg |= AUTH_ALG_AES << AUTH_ALG_SHIFT;
104 else
105 cfg |= AUTH_ALG_SHA << AUTH_ALG_SHIFT;

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136
137 if (IS_CBC(flags) || IS_CTR(flags) || IS_CCM(flags) ||
138 IS_CMAC(flags))
139 cfg |= BIT(AUTH_LAST_SHIFT) | BIT(AUTH_FIRST_SHIFT);
140
141 return cfg;
142}
143
140static u32 qce_config_reg(struct qce_device *qce, int little)
141{
142 u32 beats = (qce->burst_size >> 3) - 1;
143 u32 pipe_pair = qce->pipe_pair_id;
144 u32 config;
145
146 config = (beats << REQ_SIZE_SHIFT) & REQ_SIZE_MASK;
147 config |= BIT(MASK_DOUT_INTR_SHIFT) | BIT(MASK_DIN_INTR_SHIFT) |
148 BIT(MASK_OP_DONE_INTR_SHIFT) | BIT(MASK_ERR_INTR_SHIFT);
149 config |= (pipe_pair << PIPE_SET_SELECT_SHIFT) & PIPE_SET_SELECT_MASK;
150 config &= ~HIGH_SPD_EN_N_SHIFT;
151
152 if (little)
153 config |= BIT(LITTLE_ENDIAN_MODE_SHIFT);
154
155 return config;
156}
157
158void qce_cpu_to_be32p_array(__be32 *dst, const u8 *src, unsigned int len)
159{
160 __be32 *d = dst;
161 const u8 *s = src;
162 unsigned int n;
163
164 n = len / sizeof(u32);
165 for (; n > 0; n--) {
166 *d = cpu_to_be32p((const __u32 *) s);
167 s += sizeof(__u32);
168 d++;
169 }
170}
171
172static void qce_xts_swapiv(__be32 *dst, const u8 *src, unsigned int ivsize)
173{
174 u8 swap[QCE_AES_IV_LENGTH];
175 u32 i, j;
176
177 if (ivsize > QCE_AES_IV_LENGTH)
178 return;
179
180 memset(swap, 0, QCE_AES_IV_LENGTH);
181
182 for (i = (QCE_AES_IV_LENGTH - ivsize), j = ivsize - 1;
183 i < QCE_AES_IV_LENGTH; i++, j--)
184 swap[i] = src[j];
185
186 qce_cpu_to_be32p_array(dst, swap, QCE_AES_IV_LENGTH);
187}
188
189static void qce_xtskey(struct qce_device *qce, const u8 *enckey,
190 unsigned int enckeylen, unsigned int cryptlen)
191{
192 u32 xtskey[QCE_MAX_CIPHER_KEY_SIZE / sizeof(u32)] = {0};
193 unsigned int xtsklen = enckeylen / (2 * sizeof(u32));
194 unsigned int xtsdusize;
195
196 qce_cpu_to_be32p_array((__be32 *)xtskey, enckey + enckeylen / 2,
197 enckeylen / 2);
198 qce_write_array(qce, REG_ENCR_XTS_KEY0, xtskey, xtsklen);
199
200 /* xts du size 512B */
201 xtsdusize = min_t(u32, QCE_SECTOR_SIZE, cryptlen);
202 qce_write(qce, REG_ENCR_XTS_DU_SIZE, xtsdusize);
203}
204
205static void qce_setup_config(struct qce_device *qce)
206{
207 u32 config;
208
209 /* get big endianness */
210 config = qce_config_reg(qce, 0);
211
212 /* clear status */
213 qce_write(qce, REG_STATUS, 0);
214 qce_write(qce, REG_CONFIG, config);
215}
216
217static inline void qce_crypto_go(struct qce_device *qce)
218{
219 qce_write(qce, REG_GOPROC, BIT(GO_SHIFT) | BIT(RESULTS_DUMP_SHIFT));
220}
221
222static int qce_setup_regs_ahash(struct crypto_async_request *async_req,
223 u32 totallen, u32 offset)
224{
225 struct ahash_request *req = ahash_request_cast(async_req);
226 struct crypto_ahash *ahash = __crypto_ahash_cast(async_req->tfm);
227 struct qce_sha_reqctx *rctx = ahash_request_ctx(req);
228 struct qce_alg_template *tmpl = to_ahash_tmpl(async_req->tfm);
229 struct qce_device *qce = tmpl->qce;

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298 /* get little endianness */
299 config = qce_config_reg(qce, 1);
300 qce_write(qce, REG_CONFIG, config);
301
302 qce_crypto_go(qce);
303
304 return 0;
305}
144static int qce_setup_regs_ahash(struct crypto_async_request *async_req,
145 u32 totallen, u32 offset)
146{
147 struct ahash_request *req = ahash_request_cast(async_req);
148 struct crypto_ahash *ahash = __crypto_ahash_cast(async_req->tfm);
149 struct qce_sha_reqctx *rctx = ahash_request_ctx(req);
150 struct qce_alg_template *tmpl = to_ahash_tmpl(async_req->tfm);
151 struct qce_device *qce = tmpl->qce;

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220 /* get little endianness */
221 config = qce_config_reg(qce, 1);
222 qce_write(qce, REG_CONFIG, config);
223
224 qce_crypto_go(qce);
225
226 return 0;
227}
228#endif
306
229
230#ifdef CONFIG_CRYPTO_DEV_QCE_SKCIPHER
231static u32 qce_encr_cfg(unsigned long flags, u32 aes_key_size)
232{
233 u32 cfg = 0;
234
235 if (IS_AES(flags)) {
236 if (aes_key_size == AES_KEYSIZE_128)
237 cfg |= ENCR_KEY_SZ_AES128 << ENCR_KEY_SZ_SHIFT;
238 else if (aes_key_size == AES_KEYSIZE_256)
239 cfg |= ENCR_KEY_SZ_AES256 << ENCR_KEY_SZ_SHIFT;
240 }
241
242 if (IS_AES(flags))
243 cfg |= ENCR_ALG_AES << ENCR_ALG_SHIFT;
244 else if (IS_DES(flags) || IS_3DES(flags))
245 cfg |= ENCR_ALG_DES << ENCR_ALG_SHIFT;
246
247 if (IS_DES(flags))
248 cfg |= ENCR_KEY_SZ_DES << ENCR_KEY_SZ_SHIFT;
249
250 if (IS_3DES(flags))
251 cfg |= ENCR_KEY_SZ_3DES << ENCR_KEY_SZ_SHIFT;
252
253 switch (flags & QCE_MODE_MASK) {
254 case QCE_MODE_ECB:
255 cfg |= ENCR_MODE_ECB << ENCR_MODE_SHIFT;
256 break;
257 case QCE_MODE_CBC:
258 cfg |= ENCR_MODE_CBC << ENCR_MODE_SHIFT;
259 break;
260 case QCE_MODE_CTR:
261 cfg |= ENCR_MODE_CTR << ENCR_MODE_SHIFT;
262 break;
263 case QCE_MODE_XTS:
264 cfg |= ENCR_MODE_XTS << ENCR_MODE_SHIFT;
265 break;
266 case QCE_MODE_CCM:
267 cfg |= ENCR_MODE_CCM << ENCR_MODE_SHIFT;
268 cfg |= LAST_CCM_XFR << LAST_CCM_SHIFT;
269 break;
270 default:
271 return ~0;
272 }
273
274 return cfg;
275}
276
277static void qce_xts_swapiv(__be32 *dst, const u8 *src, unsigned int ivsize)
278{
279 u8 swap[QCE_AES_IV_LENGTH];
280 u32 i, j;
281
282 if (ivsize > QCE_AES_IV_LENGTH)
283 return;
284
285 memset(swap, 0, QCE_AES_IV_LENGTH);
286
287 for (i = (QCE_AES_IV_LENGTH - ivsize), j = ivsize - 1;
288 i < QCE_AES_IV_LENGTH; i++, j--)
289 swap[i] = src[j];
290
291 qce_cpu_to_be32p_array(dst, swap, QCE_AES_IV_LENGTH);
292}
293
294static void qce_xtskey(struct qce_device *qce, const u8 *enckey,
295 unsigned int enckeylen, unsigned int cryptlen)
296{
297 u32 xtskey[QCE_MAX_CIPHER_KEY_SIZE / sizeof(u32)] = {0};
298 unsigned int xtsklen = enckeylen / (2 * sizeof(u32));
299 unsigned int xtsdusize;
300
301 qce_cpu_to_be32p_array((__be32 *)xtskey, enckey + enckeylen / 2,
302 enckeylen / 2);
303 qce_write_array(qce, REG_ENCR_XTS_KEY0, xtskey, xtsklen);
304
305 /* xts du size 512B */
306 xtsdusize = min_t(u32, QCE_SECTOR_SIZE, cryptlen);
307 qce_write(qce, REG_ENCR_XTS_DU_SIZE, xtsdusize);
308}
309
307static int qce_setup_regs_skcipher(struct crypto_async_request *async_req,
308 u32 totallen, u32 offset)
309{
310 struct skcipher_request *req = skcipher_request_cast(async_req);
311 struct qce_cipher_reqctx *rctx = skcipher_request_ctx(req);
312 struct qce_cipher_ctx *ctx = crypto_tfm_ctx(async_req->tfm);
313 struct qce_alg_template *tmpl = to_cipher_tmpl(crypto_skcipher_reqtfm(req));
314 struct qce_device *qce = tmpl->qce;

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379 /* get little endianness */
380 config = qce_config_reg(qce, 1);
381 qce_write(qce, REG_CONFIG, config);
382
383 qce_crypto_go(qce);
384
385 return 0;
386}
310static int qce_setup_regs_skcipher(struct crypto_async_request *async_req,
311 u32 totallen, u32 offset)
312{
313 struct skcipher_request *req = skcipher_request_cast(async_req);
314 struct qce_cipher_reqctx *rctx = skcipher_request_ctx(req);
315 struct qce_cipher_ctx *ctx = crypto_tfm_ctx(async_req->tfm);
316 struct qce_alg_template *tmpl = to_cipher_tmpl(crypto_skcipher_reqtfm(req));
317 struct qce_device *qce = tmpl->qce;

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382 /* get little endianness */
383 config = qce_config_reg(qce, 1);
384 qce_write(qce, REG_CONFIG, config);
385
386 qce_crypto_go(qce);
387
388 return 0;
389}
390#endif
387
388int qce_start(struct crypto_async_request *async_req, u32 type, u32 totallen,
389 u32 offset)
390{
391 switch (type) {
391
392int qce_start(struct crypto_async_request *async_req, u32 type, u32 totallen,
393 u32 offset)
394{
395 switch (type) {
396#ifdef CONFIG_CRYPTO_DEV_QCE_SKCIPHER
392 case CRYPTO_ALG_TYPE_SKCIPHER:
393 return qce_setup_regs_skcipher(async_req, totallen, offset);
397 case CRYPTO_ALG_TYPE_SKCIPHER:
398 return qce_setup_regs_skcipher(async_req, totallen, offset);
399#endif
400#ifdef CONFIG_CRYPTO_DEV_QCE_SHA
394 case CRYPTO_ALG_TYPE_AHASH:
395 return qce_setup_regs_ahash(async_req, totallen, offset);
401 case CRYPTO_ALG_TYPE_AHASH:
402 return qce_setup_regs_ahash(async_req, totallen, offset);
403#endif
396 default:
397 return -EINVAL;
398 }
399}
400
401#define STATUS_ERRORS \
402 (BIT(SW_ERR_SHIFT) | BIT(AXI_ERR_SHIFT) | BIT(HSD_ERR_SHIFT))
403

--- 27 unchanged lines hidden --- 		404 default:
405 return -EINVAL;
406 }
407}
408
409#define STATUS_ERRORS \
410 (BIT(SW_ERR_SHIFT) | BIT(AXI_ERR_SHIFT) | BIT(HSD_ERR_SHIFT))
411

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