regs.h (e9331ee9b164d58b4dd0abc882ba7e23d2f404b3) regs.h (c056d910f08029662080a01b4ce2110e2c9a27b6)
1/*
2 * CAAM hardware register-level view
3 *
4 * Copyright 2008-2011 Freescale Semiconductor, Inc.
5 */
6
7#ifndef REGS_H
8#define REGS_H

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62 * that 32 bits, the hardware employs logic to latch the other
63 * "half" of the data until read, ensuring an accurate value.
64 * This is of particular relevance when dealing with CAAM's
65 * performance counters.
66 *
67 */
68
69extern bool caam_little_end;
1/*
2 * CAAM hardware register-level view
3 *
4 * Copyright 2008-2011 Freescale Semiconductor, Inc.
5 */
6
7#ifndef REGS_H
8#define REGS_H

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62 * that 32 bits, the hardware employs logic to latch the other
63 * "half" of the data until read, ensuring an accurate value.
64 * This is of particular relevance when dealing with CAAM's
65 * performance counters.
66 *
67 */
68
69extern bool caam_little_end;
70extern bool caam_imx;
70
71#define caam_to_cpu(len) \
72static inline u##len caam##len ## _to_cpu(u##len val) \
73{ \
74 if (caam_little_end) \
75 return le##len ## _to_cpu(val); \
76 else \
77 return be##len ## _to_cpu(val); \

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149 return ioread64(reg);
150 else
151 return ioread64be(reg);
152}
153
154#else /* CONFIG_64BIT */
155static inline void wr_reg64(void __iomem *reg, u64 data)
156{
71
72#define caam_to_cpu(len) \
73static inline u##len caam##len ## _to_cpu(u##len val) \
74{ \
75 if (caam_little_end) \
76 return le##len ## _to_cpu(val); \
77 else \
78 return be##len ## _to_cpu(val); \

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150 return ioread64(reg);
151 else
152 return ioread64be(reg);
153}
154
155#else /* CONFIG_64BIT */
156static inline void wr_reg64(void __iomem *reg, u64 data)
157{
157#ifndef CONFIG_CRYPTO_DEV_FSL_CAAM_IMX
158 if (caam_little_end) {
158 if (!caam_imx && caam_little_end) {
159 wr_reg32((u32 __iomem *)(reg) + 1, data >> 32);
160 wr_reg32((u32 __iomem *)(reg), data);
159 wr_reg32((u32 __iomem *)(reg) + 1, data >> 32);
160 wr_reg32((u32 __iomem *)(reg), data);
161 } else
162#endif
163 {
161 } else {
164 wr_reg32((u32 __iomem *)(reg), data >> 32);
165 wr_reg32((u32 __iomem *)(reg) + 1, data);
166 }
167}
168
169static inline u64 rd_reg64(void __iomem *reg)
170{
162 wr_reg32((u32 __iomem *)(reg), data >> 32);
163 wr_reg32((u32 __iomem *)(reg) + 1, data);
164 }
165}
166
167static inline u64 rd_reg64(void __iomem *reg)
168{
171#ifndef CONFIG_CRYPTO_DEV_FSL_CAAM_IMX
172 if (caam_little_end)
169 if (!caam_imx && caam_little_end)
173 return ((u64)rd_reg32((u32 __iomem *)(reg) + 1) << 32 |
174 (u64)rd_reg32((u32 __iomem *)(reg)));
170 return ((u64)rd_reg32((u32 __iomem *)(reg) + 1) << 32 |
171 (u64)rd_reg32((u32 __iomem *)(reg)));
175 else
176#endif
177 return ((u64)rd_reg32((u32 __iomem *)(reg)) << 32 |
178 (u64)rd_reg32((u32 __iomem *)(reg) + 1));
172
173 return ((u64)rd_reg32((u32 __iomem *)(reg)) << 32 |
174 (u64)rd_reg32((u32 __iomem *)(reg) + 1));
179}
180#endif /* CONFIG_64BIT */
181
175}
176#endif /* CONFIG_64BIT */
177
178static inline u64 cpu_to_caam_dma64(dma_addr_t value)
179{
180 if (caam_imx)
181 return (((u64)cpu_to_caam32(lower_32_bits(value)) << 32) |
182 (u64)cpu_to_caam32(upper_32_bits(value)));
183
184 return cpu_to_caam64(value);
185}
186
187static inline u64 caam_dma64_to_cpu(u64 value)
188{
189 if (caam_imx)
190 return (((u64)caam32_to_cpu(lower_32_bits(value)) << 32) |
191 (u64)caam32_to_cpu(upper_32_bits(value)));
192
193 return caam64_to_cpu(value);
194}
195
182#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
196#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
183#ifdef CONFIG_SOC_IMX7D
184#define cpu_to_caam_dma(value) \
185 (((u64)cpu_to_caam32(lower_32_bits(value)) << 32) | \
186 (u64)cpu_to_caam32(upper_32_bits(value)))
187#define caam_dma_to_cpu(value) \
188 (((u64)caam32_to_cpu(lower_32_bits(value)) << 32) | \
189 (u64)caam32_to_cpu(upper_32_bits(value)))
197#define cpu_to_caam_dma(value) cpu_to_caam_dma64(value)
198#define caam_dma_to_cpu(value) caam_dma64_to_cpu(value)
190#else
199#else
191#define cpu_to_caam_dma(value) cpu_to_caam64(value)
192#define caam_dma_to_cpu(value) caam64_to_cpu(value)
193#endif /* CONFIG_SOC_IMX7D */
194#else
195#define cpu_to_caam_dma(value) cpu_to_caam32(value)
196#define caam_dma_to_cpu(value) caam32_to_cpu(value)
200#define cpu_to_caam_dma(value) cpu_to_caam32(value)
201#define caam_dma_to_cpu(value) caam32_to_cpu(value)
197#endif /* CONFIG_ARCH_DMA_ADDR_T_64BIT */
202#endif /* CONFIG_ARCH_DMA_ADDR_T_64BIT */
198
203
199#ifdef CONFIG_CRYPTO_DEV_FSL_CAAM_IMX
200#define cpu_to_caam_dma64(value) \
201 (((u64)cpu_to_caam32(lower_32_bits(value)) << 32) | \
202 (u64)cpu_to_caam32(upper_32_bits(value)))
203#else
204#define cpu_to_caam_dma64(value) cpu_to_caam64(value)
205#endif
206
207/*
208 * jr_outentry
209 * Represents each entry in a JobR output ring
210 */
211struct jr_outentry {
212 dma_addr_t desc;/* Pointer to completed descriptor */
213 u32 jrstatus; /* Status for completed descriptor */
214} __packed;

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205 * jr_outentry
206 * Represents each entry in a JobR output ring
207 */
208struct jr_outentry {
209 dma_addr_t desc;/* Pointer to completed descriptor */
210 u32 jrstatus; /* Status for completed descriptor */
211} __packed;

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