desc.h (1f06ec1d48f31a454e4292f3761a4f4178bb916c) desc.h (6c3af955935223217f23ef0ae672d3842418ec50)
1/*
2 * CAAM descriptor composition header
3 * Definitions to support CAAM descriptor instruction generation
4 *
5 * Copyright 2008-2011 Freescale Semiconductor, Inc.
6 */
7
8#ifndef DESC_H

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18#define SEC4_SG_LEN_EXT 0x80000000 /* Entry points to table */
19#define SEC4_SG_LEN_FIN 0x40000000 /* Last ent in table */
20#define SEC4_SG_BPID_MASK 0x000000ff
21#define SEC4_SG_BPID_SHIFT 16
22#define SEC4_SG_LEN_MASK 0x3fffffff /* Excludes EXT and FINAL */
23#define SEC4_SG_OFFS_MASK 0x00001fff
24
25struct sec4_sg_entry {
1/*
2 * CAAM descriptor composition header
3 * Definitions to support CAAM descriptor instruction generation
4 *
5 * Copyright 2008-2011 Freescale Semiconductor, Inc.
6 */
7
8#ifndef DESC_H

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18#define SEC4_SG_LEN_EXT 0x80000000 /* Entry points to table */
19#define SEC4_SG_LEN_FIN 0x40000000 /* Last ent in table */
20#define SEC4_SG_BPID_MASK 0x000000ff
21#define SEC4_SG_BPID_SHIFT 16
22#define SEC4_SG_LEN_MASK 0x3fffffff /* Excludes EXT and FINAL */
23#define SEC4_SG_OFFS_MASK 0x00001fff
24
25struct sec4_sg_entry {
26#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
27 dma_addr_t ptr;
28#else
26#ifdef CONFIG_CRYPTO_DEV_FSL_CAAM_IMX
29 u32 rsvd1;
30 dma_addr_t ptr;
27 u32 rsvd1;
28 dma_addr_t ptr;
31#endif
29#else
30 u64 ptr;
31#endif /* CONFIG_CRYPTO_DEV_FSL_CAAM_IMX */
32 u32 len;
33 u8 rsvd2;
34 u8 buf_pool_id;
35 u16 offset;
36};
37
38/* Max size of any CAAM descriptor in 32-bit words, inclusive of header */
39#define MAX_CAAM_DESCSIZE 64

--- 1599 unchanged lines hidden --- 		32 u32 len;
33 u8 rsvd2;
34 u8 buf_pool_id;
35 u16 offset;
36};
37
38/* Max size of any CAAM descriptor in 32-bit words, inclusive of header */
39#define MAX_CAAM_DESCSIZE 64

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