ctrl.c (8dd06ef34b6e2f41b29fbf5fc1663780f2524285) ctrl.c (24c7bf089453f6a1eed4c77ed0604bf4bb8cfb03)
1// SPDX-License-Identifier: GPL-2.0+
2/* * CAAM control-plane driver backend
3 * Controller-level driver, kernel property detection, initialization
4 *
5 * Copyright 2008-2012 Freescale Semiconductor, Inc.
6 * Copyright 2018-2019 NXP
7 */
8
9#include <linux/device.h>
10#include <linux/of_address.h>
11#include <linux/of_irq.h>
12#include <linux/sys_soc.h>
1// SPDX-License-Identifier: GPL-2.0+
2/* * CAAM control-plane driver backend
3 * Controller-level driver, kernel property detection, initialization
4 *
5 * Copyright 2008-2012 Freescale Semiconductor, Inc.
6 * Copyright 2018-2019 NXP
7 */
8
9#include <linux/device.h>
10#include <linux/of_address.h>
11#include <linux/of_irq.h>
12#include <linux/sys_soc.h>
13#include <linux/fsl/mc.h>
13
14#include "compat.h"
15#include "regs.h"
16#include "intern.h"
17#include "jr.h"
18#include "desc_constr.h"
19#include "ctrl.h"
20

--- 10 unchanged lines hidden (view full) ---

31 */
32static void build_instantiation_desc(u32 *desc, int handle, int do_sk)
33{
34 u32 *jump_cmd, op_flags;
35
36 init_job_desc(desc, 0);
37
38 op_flags = OP_TYPE_CLASS1_ALG | OP_ALG_ALGSEL_RNG |
14
15#include "compat.h"
16#include "regs.h"
17#include "intern.h"
18#include "jr.h"
19#include "desc_constr.h"
20#include "ctrl.h"
21

--- 10 unchanged lines hidden (view full) ---

32 */
33static void build_instantiation_desc(u32 *desc, int handle, int do_sk)
34{
35 u32 *jump_cmd, op_flags;
36
37 init_job_desc(desc, 0);
38
39 op_flags = OP_TYPE_CLASS1_ALG | OP_ALG_ALGSEL_RNG |
39 (handle << OP_ALG_AAI_SHIFT) | OP_ALG_AS_INIT;
40 (handle << OP_ALG_AAI_SHIFT) | OP_ALG_AS_INIT |
41 OP_ALG_PR_ON;
40
41 /* INIT RNG in non-test mode */
42 append_operation(desc, op_flags);
43
44 if (!handle && do_sk) {
45 /*
46 * For SH0, Secure Keys must be generated as well
47 */
48
49 /* wait for done */
50 jump_cmd = append_jump(desc, JUMP_CLASS_CLASS1);
51 set_jump_tgt_here(desc, jump_cmd);
52
53 /*
54 * load 1 to clear written reg:
42
43 /* INIT RNG in non-test mode */
44 append_operation(desc, op_flags);
45
46 if (!handle && do_sk) {
47 /*
48 * For SH0, Secure Keys must be generated as well
49 */
50
51 /* wait for done */
52 jump_cmd = append_jump(desc, JUMP_CLASS_CLASS1);
53 set_jump_tgt_here(desc, jump_cmd);
54
55 /*
56 * load 1 to clear written reg:
55 * resets the done interrrupt and returns the RNG to idle.
57 * resets the done interrupt and returns the RNG to idle.
56 */
57 append_load_imm_u32(desc, 1, LDST_SRCDST_WORD_CLRW);
58
59 /* Initialize State Handle */
60 append_operation(desc, OP_TYPE_CLASS1_ALG | OP_ALG_ALGSEL_RNG |
61 OP_ALG_AAI_RNG4_SK);
62 }
63

--- 85 unchanged lines hidden (view full) ---

149 deco_state = (deco_dbg_reg & DESC_DBG_DECO_STAT_MASK) >>
150 DESC_DBG_DECO_STAT_SHIFT;
151 else
152 deco_state = (rd_reg32(&deco->dbg_exec) &
153 DESC_DER_DECO_STAT_MASK) >>
154 DESC_DER_DECO_STAT_SHIFT;
155
156 /*
58 */
59 append_load_imm_u32(desc, 1, LDST_SRCDST_WORD_CLRW);
60
61 /* Initialize State Handle */
62 append_operation(desc, OP_TYPE_CLASS1_ALG | OP_ALG_ALGSEL_RNG |
63 OP_ALG_AAI_RNG4_SK);
64 }
65

--- 85 unchanged lines hidden (view full) ---

151 deco_state = (deco_dbg_reg & DESC_DBG_DECO_STAT_MASK) >>
152 DESC_DBG_DECO_STAT_SHIFT;
153 else
154 deco_state = (rd_reg32(&deco->dbg_exec) &
155 DESC_DER_DECO_STAT_MASK) >>
156 DESC_DER_DECO_STAT_SHIFT;
157
158 /*
157 * If an error occured in the descriptor, then
159 * If an error occurred in the descriptor, then
158 * the DECO status field will be set to 0x0D
159 */
160 if (deco_state == DECO_STAT_HOST_ERR)
161 break;
162
163 cpu_relax();
164 } while ((deco_dbg_reg & DESC_DBG_DECO_STAT_VALID) && --timeout);
165

--- 25 unchanged lines hidden (view full) ---

191 * - -ENODEV if DECO0 couldn't be acquired
192 * - -EAGAIN if an error occurred when executing the descriptor
193 */
194static int deinstantiate_rng(struct device *ctrldev, int state_handle_mask)
195{
196 u32 *desc, status;
197 int sh_idx, ret = 0;
198
160 * the DECO status field will be set to 0x0D
161 */
162 if (deco_state == DECO_STAT_HOST_ERR)
163 break;
164
165 cpu_relax();
166 } while ((deco_dbg_reg & DESC_DBG_DECO_STAT_VALID) && --timeout);
167

--- 25 unchanged lines hidden (view full) ---

193 * - -ENODEV if DECO0 couldn't be acquired
194 * - -EAGAIN if an error occurred when executing the descriptor
195 */
196static int deinstantiate_rng(struct device *ctrldev, int state_handle_mask)
197{
198 u32 *desc, status;
199 int sh_idx, ret = 0;
200
199 desc = kmalloc(CAAM_CMD_SZ * 3, GFP_KERNEL);
201 desc = kmalloc(CAAM_CMD_SZ * 3, GFP_KERNEL | GFP_DMA);
200 if (!desc)
201 return -ENOMEM;
202
203 for (sh_idx = 0; sh_idx < RNG4_MAX_HANDLES; sh_idx++) {
204 /*
205 * If the corresponding bit is set, then it means the state
206 * handle was initialized by us, and thus it needs to be
207 * deinitialized as well

--- 49 unchanged lines hidden (view full) ---

257 * Caution: this can be done only once; if the keys need to be
258 * regenerated, a POR is required
259 *
260 * Return: - 0 if no error occurred
261 * - -ENOMEM if there isn't enough memory to allocate the descriptor
262 * - -ENODEV if DECO0 couldn't be acquired
263 * - -EAGAIN if an error occurred when executing the descriptor
264 * f.i. there was a RNG hardware error due to not "good enough"
202 if (!desc)
203 return -ENOMEM;
204
205 for (sh_idx = 0; sh_idx < RNG4_MAX_HANDLES; sh_idx++) {
206 /*
207 * If the corresponding bit is set, then it means the state
208 * handle was initialized by us, and thus it needs to be
209 * deinitialized as well

--- 49 unchanged lines hidden (view full) ---

259 * Caution: this can be done only once; if the keys need to be
260 * regenerated, a POR is required
261 *
262 * Return: - 0 if no error occurred
263 * - -ENOMEM if there isn't enough memory to allocate the descriptor
264 * - -ENODEV if DECO0 couldn't be acquired
265 * - -EAGAIN if an error occurred when executing the descriptor
266 * f.i. there was a RNG hardware error due to not "good enough"
265 * entropy being aquired.
267 * entropy being acquired.
266 */
267static int instantiate_rng(struct device *ctrldev, int state_handle_mask,
268 int gen_sk)
269{
270 struct caam_drv_private *ctrlpriv = dev_get_drvdata(ctrldev);
271 struct caam_ctrl __iomem *ctrl;
272 u32 *desc, status = 0, rdsta_val;
273 int ret = 0, sh_idx;
274
275 ctrl = (struct caam_ctrl __iomem *)ctrlpriv->ctrl;
268 */
269static int instantiate_rng(struct device *ctrldev, int state_handle_mask,
270 int gen_sk)
271{
272 struct caam_drv_private *ctrlpriv = dev_get_drvdata(ctrldev);
273 struct caam_ctrl __iomem *ctrl;
274 u32 *desc, status = 0, rdsta_val;
275 int ret = 0, sh_idx;
276
277 ctrl = (struct caam_ctrl __iomem *)ctrlpriv->ctrl;
276 desc = kmalloc(CAAM_CMD_SZ * 7, GFP_KERNEL);
278 desc = kmalloc(CAAM_CMD_SZ * 7, GFP_KERNEL | GFP_DMA);
277 if (!desc)
278 return -ENOMEM;
279
280 for (sh_idx = 0; sh_idx < RNG4_MAX_HANDLES; sh_idx++) {
279 if (!desc)
280 return -ENOMEM;
281
282 for (sh_idx = 0; sh_idx < RNG4_MAX_HANDLES; sh_idx++) {
283 const u32 rdsta_if = RDSTA_IF0 << sh_idx;
284 const u32 rdsta_pr = RDSTA_PR0 << sh_idx;
285 const u32 rdsta_mask = rdsta_if | rdsta_pr;
281 /*
282 * If the corresponding bit is set, this state handle
283 * was initialized by somebody else, so it's left alone.
284 */
286 /*
287 * If the corresponding bit is set, this state handle
288 * was initialized by somebody else, so it's left alone.
289 */
285 if ((1 << sh_idx) & state_handle_mask)
286 continue;
290 if (rdsta_if & state_handle_mask) {
291 if (rdsta_pr & state_handle_mask)
292 continue;
287
293
294 dev_info(ctrldev,
295 "RNG4 SH%d was previously instantiated without prediction resistance. Tearing it down\n",
296 sh_idx);
297
298 ret = deinstantiate_rng(ctrldev, rdsta_if);
299 if (ret)
300 break;
301 }
302
288 /* Create the descriptor for instantiating RNG State Handle */
289 build_instantiation_desc(desc, sh_idx, gen_sk);
290
291 /* Try to run it through DECO0 */
292 ret = run_descriptor_deco0(ctrldev, desc, &status);
293
294 /*
295 * If ret is not 0, or descriptor status is not 0, then
296 * something went wrong. No need to try the next state
297 * handle (if available), bail out here.
298 * Also, if for some reason, the State Handle didn't get
299 * instantiated although the descriptor has finished
300 * without any error (HW optimizations for later
301 * CAAM eras), then try again.
302 */
303 if (ret)
304 break;
305
303 /* Create the descriptor for instantiating RNG State Handle */
304 build_instantiation_desc(desc, sh_idx, gen_sk);
305
306 /* Try to run it through DECO0 */
307 ret = run_descriptor_deco0(ctrldev, desc, &status);
308
309 /*
310 * If ret is not 0, or descriptor status is not 0, then
311 * something went wrong. No need to try the next state
312 * handle (if available), bail out here.
313 * Also, if for some reason, the State Handle didn't get
314 * instantiated although the descriptor has finished
315 * without any error (HW optimizations for later
316 * CAAM eras), then try again.
317 */
318 if (ret)
319 break;
320
306 rdsta_val = rd_reg32(&ctrl->r4tst[0].rdsta) & RDSTA_IFMASK;
321 rdsta_val = rd_reg32(&ctrl->r4tst[0].rdsta) & RDSTA_MASK;
307 if ((status && status != JRSTA_SSRC_JUMP_HALT_CC) ||
322 if ((status && status != JRSTA_SSRC_JUMP_HALT_CC) ||
308 !(rdsta_val & (1 << sh_idx))) {
323 (rdsta_val & rdsta_mask) != rdsta_mask) {
309 ret = -EAGAIN;
310 break;
311 }
312
313 dev_info(ctrldev, "Instantiated RNG4 SH%d\n", sh_idx);
314 /* Clear the contents before recreating the descriptor */
315 memset(desc, 0x00, CAAM_CMD_SZ * 7);
316 }

--- 19 unchanged lines hidden (view full) ---

336 struct caam_drv_private *ctrlpriv = dev_get_drvdata(ctrldev);
337 struct caam_ctrl __iomem *ctrl;
338 struct rng4tst __iomem *r4tst;
339 u32 val;
340
341 ctrl = (struct caam_ctrl __iomem *)ctrlpriv->ctrl;
342 r4tst = &ctrl->r4tst[0];
343
324 ret = -EAGAIN;
325 break;
326 }
327
328 dev_info(ctrldev, "Instantiated RNG4 SH%d\n", sh_idx);
329 /* Clear the contents before recreating the descriptor */
330 memset(desc, 0x00, CAAM_CMD_SZ * 7);
331 }

--- 19 unchanged lines hidden (view full) ---

351 struct caam_drv_private *ctrlpriv = dev_get_drvdata(ctrldev);
352 struct caam_ctrl __iomem *ctrl;
353 struct rng4tst __iomem *r4tst;
354 u32 val;
355
356 ctrl = (struct caam_ctrl __iomem *)ctrlpriv->ctrl;
357 r4tst = &ctrl->r4tst[0];
358
344 /* put RNG4 into program mode */
345 clrsetbits_32(&r4tst->rtmctl, 0, RTMCTL_PRGM);
359 /*
360 * Setting both RTMCTL:PRGM and RTMCTL:TRNG_ACC causes TRNG to
361 * properly invalidate the entropy in the entropy register and
362 * force re-generation.
363 */
364 clrsetbits_32(&r4tst->rtmctl, 0, RTMCTL_PRGM | RTMCTL_ACC);
346
347 /*
348 * Performance-wise, it does not make sense to
349 * set the delay to a value that is lower
350 * than the last one that worked (i.e. the state handles
351 * were instantiated properly. Thus, instead of wasting
352 * time trying to set the values controlling the sample
353 * frequency, the function simply returns.

--- 13 unchanged lines hidden (view full) ---

367 wr_reg32(&r4tst->rtfrqmax, RTFRQMAX_DISABLE);
368 /* read the control register */
369 val = rd_reg32(&r4tst->rtmctl);
370start_rng:
371 /*
372 * select raw sampling in both entropy shifter
373 * and statistical checker; ; put RNG4 into run mode
374 */
365
366 /*
367 * Performance-wise, it does not make sense to
368 * set the delay to a value that is lower
369 * than the last one that worked (i.e. the state handles
370 * were instantiated properly. Thus, instead of wasting
371 * time trying to set the values controlling the sample
372 * frequency, the function simply returns.

--- 13 unchanged lines hidden (view full) ---

386 wr_reg32(&r4tst->rtfrqmax, RTFRQMAX_DISABLE);
387 /* read the control register */
388 val = rd_reg32(&r4tst->rtmctl);
389start_rng:
390 /*
391 * select raw sampling in both entropy shifter
392 * and statistical checker; ; put RNG4 into run mode
393 */
375 clrsetbits_32(&r4tst->rtmctl, RTMCTL_PRGM, RTMCTL_SAMP_MODE_RAW_ES_SC);
394 clrsetbits_32(&r4tst->rtmctl, RTMCTL_PRGM | RTMCTL_ACC,
395 RTMCTL_SAMP_MODE_RAW_ES_SC);
376}
377
378static int caam_get_era_from_hw(struct caam_ctrl __iomem *ctrl)
379{
380 static const struct {
381 u16 ip_id;
382 u8 maj_rev;
383 u8 era;

--- 170 unchanged lines hidden (view full) ---

554
555#ifdef CONFIG_DEBUG_FS
556static void caam_remove_debugfs(void *root)
557{
558 debugfs_remove_recursive(root);
559}
560#endif
561
396}
397
398static int caam_get_era_from_hw(struct caam_ctrl __iomem *ctrl)
399{
400 static const struct {
401 u16 ip_id;
402 u8 maj_rev;
403 u8 era;

--- 170 unchanged lines hidden (view full) ---

574
575#ifdef CONFIG_DEBUG_FS
576static void caam_remove_debugfs(void *root)
577{
578 debugfs_remove_recursive(root);
579}
580#endif
581
582#ifdef CONFIG_FSL_MC_BUS
583static bool check_version(struct fsl_mc_version *mc_version, u32 major,
584 u32 minor, u32 revision)
585{
586 if (mc_version->major > major)
587 return true;
588
589 if (mc_version->major == major) {
590 if (mc_version->minor > minor)
591 return true;
592
593 if (mc_version->minor == minor &&
594 mc_version->revision > revision)
595 return true;
596 }
597
598 return false;
599}
600#endif
601
562/* Probe routine for CAAM top (controller) level */
563static int caam_probe(struct platform_device *pdev)
564{
565 int ret, ring, gen_sk, ent_delay = RTSDCTL_ENT_DLY_MIN;
566 u64 caam_id;
567 const struct soc_device_attribute *imx_soc_match;
568 struct device *dev;
569 struct device_node *nprop, *np;
570 struct caam_ctrl __iomem *ctrl;
571 struct caam_drv_private *ctrlpriv;
572#ifdef CONFIG_DEBUG_FS
573 struct caam_perfmon *perfmon;
574 struct dentry *dfs_root;
575#endif
576 u32 scfgr, comp_params;
577 u8 rng_vid;
578 int pg_size;
579 int BLOCK_OFFSET = 0;
602/* Probe routine for CAAM top (controller) level */
603static int caam_probe(struct platform_device *pdev)
604{
605 int ret, ring, gen_sk, ent_delay = RTSDCTL_ENT_DLY_MIN;
606 u64 caam_id;
607 const struct soc_device_attribute *imx_soc_match;
608 struct device *dev;
609 struct device_node *nprop, *np;
610 struct caam_ctrl __iomem *ctrl;
611 struct caam_drv_private *ctrlpriv;
612#ifdef CONFIG_DEBUG_FS
613 struct caam_perfmon *perfmon;
614 struct dentry *dfs_root;
615#endif
616 u32 scfgr, comp_params;
617 u8 rng_vid;
618 int pg_size;
619 int BLOCK_OFFSET = 0;
620 bool pr_support = false;
580
581 ctrlpriv = devm_kzalloc(&pdev->dev, sizeof(*ctrlpriv), GFP_KERNEL);
582 if (!ctrlpriv)
583 return -ENOMEM;
584
585 dev = &pdev->dev;
586 dev_set_drvdata(dev, ctrlpriv);
587 nprop = pdev->dev.of_node;

--- 69 unchanged lines hidden (view full) ---

657 );
658 ctrlpriv->deco = (struct caam_deco __iomem __force *)
659 ((__force uint8_t *)ctrl +
660 BLOCK_OFFSET * DECO_BLOCK_NUMBER
661 );
662
663 /* Get the IRQ of the controller (for security violations only) */
664 ctrlpriv->secvio_irq = irq_of_parse_and_map(nprop, 0);
621
622 ctrlpriv = devm_kzalloc(&pdev->dev, sizeof(*ctrlpriv), GFP_KERNEL);
623 if (!ctrlpriv)
624 return -ENOMEM;
625
626 dev = &pdev->dev;
627 dev_set_drvdata(dev, ctrlpriv);
628 nprop = pdev->dev.of_node;

--- 69 unchanged lines hidden (view full) ---

698 );
699 ctrlpriv->deco = (struct caam_deco __iomem __force *)
700 ((__force uint8_t *)ctrl +
701 BLOCK_OFFSET * DECO_BLOCK_NUMBER
702 );
703
704 /* Get the IRQ of the controller (for security violations only) */
705 ctrlpriv->secvio_irq = irq_of_parse_and_map(nprop, 0);
706 np = of_find_compatible_node(NULL, NULL, "fsl,qoriq-mc");
707 ctrlpriv->mc_en = !!np;
708 of_node_put(np);
665
709
710#ifdef CONFIG_FSL_MC_BUS
711 if (ctrlpriv->mc_en) {
712 struct fsl_mc_version *mc_version;
713
714 mc_version = fsl_mc_get_version();
715 if (mc_version)
716 pr_support = check_version(mc_version, 10, 20, 0);
717 else
718 return -EPROBE_DEFER;
719 }
720#endif
721
666 /*
667 * Enable DECO watchdogs and, if this is a PHYS_ADDR_T_64BIT kernel,
668 * long pointers in master configuration register.
669 * In case of SoCs with Management Complex, MC f/w performs
670 * the configuration.
671 */
722 /*
723 * Enable DECO watchdogs and, if this is a PHYS_ADDR_T_64BIT kernel,
724 * long pointers in master configuration register.
725 * In case of SoCs with Management Complex, MC f/w performs
726 * the configuration.
727 */
672 np = of_find_compatible_node(NULL, NULL, "fsl,qoriq-mc");
673 ctrlpriv->mc_en = !!np;
674 of_node_put(np);
675
676 if (!ctrlpriv->mc_en)
677 clrsetbits_32(&ctrl->mcr, MCFGR_AWCACHE_MASK,
678 MCFGR_AWCACHE_CACH | MCFGR_AWCACHE_BUFF |
679 MCFGR_WDENABLE | MCFGR_LARGE_BURST);
680
681 handle_imx6_err005766(&ctrl->mcr);
682
683 /*
728 if (!ctrlpriv->mc_en)
729 clrsetbits_32(&ctrl->mcr, MCFGR_AWCACHE_MASK,
730 MCFGR_AWCACHE_CACH | MCFGR_AWCACHE_BUFF |
731 MCFGR_WDENABLE | MCFGR_LARGE_BURST);
732
733 handle_imx6_err005766(&ctrl->mcr);
734
735 /*
684 * Read the Compile Time paramters and SCFGR to determine
685 * if Virtualization is enabled for this platform
736 * Read the Compile Time parameters and SCFGR to determine
737 * if virtualization is enabled for this platform
686 */
687 scfgr = rd_reg32(&ctrl->scfgr);
688
689 ctrlpriv->virt_en = 0;
690 if (comp_params & CTPR_MS_VIRT_EN_INCL) {
691 /* VIRT_EN_INCL = 1 & VIRT_EN_POR = 1 or
692 * VIRT_EN_INCL = 1 & VIRT_EN_POR = 0 & SCFGR_VIRT_EN = 1
693 */

--- 80 unchanged lines hidden (view full) ---

774 rng_vid = (rd_reg32(&ctrl->vreg.rng) & CHA_VER_VID_MASK) >>
775 CHA_VER_VID_SHIFT;
776
777 /*
778 * If SEC has RNG version >= 4 and RNG state handle has not been
779 * already instantiated, do RNG instantiation
780 * In case of SoCs with Management Complex, RNG is managed by MC f/w.
781 */
738 */
739 scfgr = rd_reg32(&ctrl->scfgr);
740
741 ctrlpriv->virt_en = 0;
742 if (comp_params & CTPR_MS_VIRT_EN_INCL) {
743 /* VIRT_EN_INCL = 1 & VIRT_EN_POR = 1 or
744 * VIRT_EN_INCL = 1 & VIRT_EN_POR = 0 & SCFGR_VIRT_EN = 1
745 */

--- 80 unchanged lines hidden (view full) ---

826 rng_vid = (rd_reg32(&ctrl->vreg.rng) & CHA_VER_VID_MASK) >>
827 CHA_VER_VID_SHIFT;
828
829 /*
830 * If SEC has RNG version >= 4 and RNG state handle has not been
831 * already instantiated, do RNG instantiation
832 * In case of SoCs with Management Complex, RNG is managed by MC f/w.
833 */
782 if (!ctrlpriv->mc_en && rng_vid >= 4) {
834 if (!(ctrlpriv->mc_en && pr_support) && rng_vid >= 4) {
783 ctrlpriv->rng4_sh_init =
784 rd_reg32(&ctrl->r4tst[0].rdsta);
785 /*
786 * If the secure keys (TDKEK, JDKEK, TDSK), were already
787 * generated, signal this to the function that is instantiating
788 * the state handles. An error would occur if RNG4 attempts
789 * to regenerate these keys before the next POR.
790 */
791 gen_sk = ctrlpriv->rng4_sh_init & RDSTA_SKVN ? 0 : 1;
835 ctrlpriv->rng4_sh_init =
836 rd_reg32(&ctrl->r4tst[0].rdsta);
837 /*
838 * If the secure keys (TDKEK, JDKEK, TDSK), were already
839 * generated, signal this to the function that is instantiating
840 * the state handles. An error would occur if RNG4 attempts
841 * to regenerate these keys before the next POR.
842 */
843 gen_sk = ctrlpriv->rng4_sh_init & RDSTA_SKVN ? 0 : 1;
792 ctrlpriv->rng4_sh_init &= RDSTA_IFMASK;
844 ctrlpriv->rng4_sh_init &= RDSTA_MASK;
793 do {
794 int inst_handles =
795 rd_reg32(&ctrl->r4tst[0].rdsta) &
845 do {
846 int inst_handles =
847 rd_reg32(&ctrl->r4tst[0].rdsta) &
796 RDSTA_IFMASK;
848 RDSTA_MASK;
797 /*
798 * If either SH were instantiated by somebody else
799 * (e.g. u-boot) then it is assumed that the entropy
800 * parameters are properly set and thus the function
801 * setting these (kick_trng(...)) is skipped.
802 * Also, if a handle was instantiated, do not change
803 * the TRNG parameters.
804 */
805 if (!(ctrlpriv->rng4_sh_init || inst_handles)) {
806 dev_info(dev,
807 "Entropy delay = %u\n",
808 ent_delay);
809 kick_trng(pdev, ent_delay);
810 ent_delay += 400;
811 }
812 /*
813 * if instantiate_rng(...) fails, the loop will rerun
849 /*
850 * If either SH were instantiated by somebody else
851 * (e.g. u-boot) then it is assumed that the entropy
852 * parameters are properly set and thus the function
853 * setting these (kick_trng(...)) is skipped.
854 * Also, if a handle was instantiated, do not change
855 * the TRNG parameters.
856 */
857 if (!(ctrlpriv->rng4_sh_init || inst_handles)) {
858 dev_info(dev,
859 "Entropy delay = %u\n",
860 ent_delay);
861 kick_trng(pdev, ent_delay);
862 ent_delay += 400;
863 }
864 /*
865 * if instantiate_rng(...) fails, the loop will rerun
814 * and the kick_trng(...) function will modfiy the
866 * and the kick_trng(...) function will modify the
815 * upper and lower limits of the entropy sampling
867 * upper and lower limits of the entropy sampling
816 * interval, leading to a sucessful initialization of
868 * interval, leading to a successful initialization of
817 * the RNG.
818 */
819 ret = instantiate_rng(dev, inst_handles,
820 gen_sk);
821 if (ret == -EAGAIN)
822 /*
823 * if here, the loop will rerun,
824 * so don't hog the CPU
825 */
826 cpu_relax();
827 } while ((ret == -EAGAIN) && (ent_delay < RTSDCTL_ENT_DLY_MAX));
828 if (ret) {
829 dev_err(dev, "failed to instantiate RNG");
830 return ret;
831 }
832 /*
869 * the RNG.
870 */
871 ret = instantiate_rng(dev, inst_handles,
872 gen_sk);
873 if (ret == -EAGAIN)
874 /*
875 * if here, the loop will rerun,
876 * so don't hog the CPU
877 */
878 cpu_relax();
879 } while ((ret == -EAGAIN) && (ent_delay < RTSDCTL_ENT_DLY_MAX));
880 if (ret) {
881 dev_err(dev, "failed to instantiate RNG");
882 return ret;
883 }
884 /*
833 * Set handles init'ed by this module as the complement of the
834 * already initialized ones
885 * Set handles initialized by this module as the complement of
886 * the already initialized ones
835 */
887 */
836 ctrlpriv->rng4_sh_init = ~ctrlpriv->rng4_sh_init & RDSTA_IFMASK;
888 ctrlpriv->rng4_sh_init = ~ctrlpriv->rng4_sh_init & RDSTA_MASK;
837
838 /* Enable RDB bit so that RNG works faster */
839 clrsetbits_32(&ctrl->scfgr, 0, SCFGR_RDBENABLE);
840 }
841
842 /* NOTE: RTIC detection ought to go here, around Si time */
843
844 caam_id = (u64)rd_reg32(&ctrl->perfmon.caam_id_ms) << 32 |

--- 79 unchanged lines hidden --- 		889
890 /* Enable RDB bit so that RNG works faster */
891 clrsetbits_32(&ctrl->scfgr, 0, SCFGR_RDBENABLE);
892 }
893
894 /* NOTE: RTIC detection ought to go here, around Si time */
895
896 caam_id = (u64)rd_reg32(&ctrl->perfmon.caam_id_ms) << 32 |

--- 79 unchanged lines hidden ---