caamalg_qi2.h (8d818c1055013d355d36188f21c7535687374f6c) caamalg_qi2.h (226853ac3ebee425300b9a692c9cd5f9e2e72571)
1/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
2/*
3 * Copyright 2015-2016 Freescale Semiconductor Inc.
4 * Copyright 2017-2018 NXP
5 */
6
7#ifndef _CAAMALG_QI2_H_
8#define _CAAMALG_QI2_H_

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135 dma_addr_t iv_dma;
136 int qm_sg_bytes;
137 dma_addr_t qm_sg_dma;
138 unsigned int assoclen;
139 dma_addr_t assoclen_dma;
140 struct dpaa2_sg_entry sgt[0];
141};
142
1/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
2/*
3 * Copyright 2015-2016 Freescale Semiconductor Inc.
4 * Copyright 2017-2018 NXP
5 */
6
7#ifndef _CAAMALG_QI2_H_
8#define _CAAMALG_QI2_H_

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135 dma_addr_t iv_dma;
136 int qm_sg_bytes;
137 dma_addr_t qm_sg_dma;
138 unsigned int assoclen;
139 dma_addr_t assoclen_dma;
140 struct dpaa2_sg_entry sgt[0];
141};
142
143/*
144 * skcipher_edesc - s/w-extended skcipher descriptor
145 * @src_nents: number of segments in input scatterlist
146 * @dst_nents: number of segments in output scatterlist
147 * @iv_dma: dma address of iv for checking continuity and link table
148 * @qm_sg_bytes: length of dma mapped qm_sg space
149 * @qm_sg_dma: I/O virtual address of h/w link table
150 * @sgt: the h/w link table, followed by IV
151 */
152struct skcipher_edesc {
153 int src_nents;
154 int dst_nents;
155 dma_addr_t iv_dma;
156 int qm_sg_bytes;
157 dma_addr_t qm_sg_dma;
158 struct dpaa2_sg_entry sgt[0];
159};
160
143/**
144 * caam_flc - Flow Context (FLC)
145 * @flc: Flow Context options
146 * @sh_desc: Shared Descriptor
147 */
148struct caam_flc {
149 u32 flc[16];
150 u32 sh_desc[MAX_SDLEN];

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162 * @fd_flt: Frame list table defining input and output
163 * fd_flt[0] - FLE pointing to output buffer
164 * fd_flt[1] - FLE pointing to input buffer
165 * @fd_flt_dma: DMA address for the frame list table
166 * @flc: Flow Context
167 * @flc_dma: I/O virtual address of Flow Context
168 * @cbk: Callback function to invoke when job is completed
169 * @ctx: arbit context attached with request by the application
161/**
162 * caam_flc - Flow Context (FLC)
163 * @flc: Flow Context options
164 * @sh_desc: Shared Descriptor
165 */
166struct caam_flc {
167 u32 flc[16];
168 u32 sh_desc[MAX_SDLEN];

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180 * @fd_flt: Frame list table defining input and output
181 * fd_flt[0] - FLE pointing to output buffer
182 * fd_flt[1] - FLE pointing to input buffer
183 * @fd_flt_dma: DMA address for the frame list table
184 * @flc: Flow Context
185 * @flc_dma: I/O virtual address of Flow Context
186 * @cbk: Callback function to invoke when job is completed
187 * @ctx: arbit context attached with request by the application
170 * @edesc: extended descriptor; points to aead_edesc
188 * @edesc: extended descriptor; points to one of {skcipher,aead}_edesc
171 */
172struct caam_request {
173 struct dpaa2_fl_entry fd_flt[2];
174 dma_addr_t fd_flt_dma;
175 struct caam_flc *flc;
176 dma_addr_t flc_dma;
177 void (*cbk)(void *ctx, u32 err);
178 void *ctx;
179 void *edesc;
180};
181
182/**
183 * dpaa2_caam_enqueue() - enqueue a crypto request
184 * @dev: device associated with the DPSECI object
185 * @req: pointer to caam_request
186 */
187int dpaa2_caam_enqueue(struct device *dev, struct caam_request *req);
188
189#endif /* _CAAMALG_QI2_H_ */
189 */
190struct caam_request {
191 struct dpaa2_fl_entry fd_flt[2];
192 dma_addr_t fd_flt_dma;
193 struct caam_flc *flc;
194 dma_addr_t flc_dma;
195 void (*cbk)(void *ctx, u32 err);
196 void *ctx;
197 void *edesc;
198};
199
200/**
201 * dpaa2_caam_enqueue() - enqueue a crypto request
202 * @dev: device associated with the DPSECI object
203 * @req: pointer to caam_request
204 */
205int dpaa2_caam_enqueue(struct device *dev, struct caam_request *req);
206
207#endif /* _CAAMALG_QI2_H_ */