caamalg_qi2.c (ed32f8d42cee118b075e4372a55c7739a11094b2) caamalg_qi2.c (1c0ab408bb6e16285fcddc9b4ce74507081d053f)
1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
2/*
3 * Copyright 2015-2016 Freescale Semiconductor Inc.
4 * Copyright 2017-2019 NXP
5 */
6
7#include "compat.h"
8#include "regs.h"
9#include "caamalg_qi2.h"
10#include "dpseci_cmd.h"
11#include "desc_constr.h"
12#include "error.h"
13#include "sg_sw_sec4.h"
14#include "sg_sw_qm2.h"
15#include "key_gen.h"
16#include "caamalg_desc.h"
17#include "caamhash_desc.h"
1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
2/*
3 * Copyright 2015-2016 Freescale Semiconductor Inc.
4 * Copyright 2017-2019 NXP
5 */
6
7#include "compat.h"
8#include "regs.h"
9#include "caamalg_qi2.h"
10#include "dpseci_cmd.h"
11#include "desc_constr.h"
12#include "error.h"
13#include "sg_sw_sec4.h"
14#include "sg_sw_qm2.h"
15#include "key_gen.h"
16#include "caamalg_desc.h"
17#include "caamhash_desc.h"
18#include "dpseci-debugfs.h"
18#include <linux/fsl/mc.h>
19#include <soc/fsl/dpaa2-io.h>
20#include <soc/fsl/dpaa2-fd.h>
21
22#define CAAM_CRA_PRIORITY 2000
23
24/* max key is sum of AES_MAX_KEY_SIZE, max split key size */
25#define CAAM_MAX_KEY_SIZE (AES_MAX_KEY_SIZE + CTR_RFC3686_NONCE_SIZE + \

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5093
5094 /* DPSECI enable */
5095 err = dpaa2_dpseci_enable(priv);
5096 if (err) {
5097 dev_err(dev, "dpaa2_dpseci_enable() failed\n");
5098 goto err_bind;
5099 }
5100
19#include <linux/fsl/mc.h>
20#include <soc/fsl/dpaa2-io.h>
21#include <soc/fsl/dpaa2-fd.h>
22
23#define CAAM_CRA_PRIORITY 2000
24
25/* max key is sum of AES_MAX_KEY_SIZE, max split key size */
26#define CAAM_MAX_KEY_SIZE (AES_MAX_KEY_SIZE + CTR_RFC3686_NONCE_SIZE + \

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5094
5095 /* DPSECI enable */
5096 err = dpaa2_dpseci_enable(priv);
5097 if (err) {
5098 dev_err(dev, "dpaa2_dpseci_enable() failed\n");
5099 goto err_bind;
5100 }
5101
5102 dpaa2_dpseci_debugfs_init(priv);
5103
5101 /* register crypto algorithms the device supports */
5102 for (i = 0; i < ARRAY_SIZE(driver_algs); i++) {
5103 struct caam_skcipher_alg *t_alg = driver_algs + i;
5104 u32 alg_sel = t_alg->caam.class1_alg_type & OP_ALG_ALGSEL_MASK;
5105
5106 /* Skip DES algorithms if not supported by device */
5107 if (!priv->sec_attr.des_acc_num &&
5108 (alg_sel == OP_ALG_ALGSEL_3DES ||

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5260{
5261 struct device *dev;
5262 struct dpaa2_caam_priv *priv;
5263 int i;
5264
5265 dev = &ls_dev->dev;
5266 priv = dev_get_drvdata(dev);
5267
5104 /* register crypto algorithms the device supports */
5105 for (i = 0; i < ARRAY_SIZE(driver_algs); i++) {
5106 struct caam_skcipher_alg *t_alg = driver_algs + i;
5107 u32 alg_sel = t_alg->caam.class1_alg_type & OP_ALG_ALGSEL_MASK;
5108
5109 /* Skip DES algorithms if not supported by device */
5110 if (!priv->sec_attr.des_acc_num &&
5111 (alg_sel == OP_ALG_ALGSEL_3DES ||

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5263{
5264 struct device *dev;
5265 struct dpaa2_caam_priv *priv;
5266 int i;
5267
5268 dev = &ls_dev->dev;
5269 priv = dev_get_drvdata(dev);
5270
5271 dpaa2_dpseci_debugfs_exit(priv);
5272
5268 for (i = 0; i < ARRAY_SIZE(driver_aeads); i++) {
5269 struct caam_aead_alg *t_alg = driver_aeads + i;
5270
5271 if (t_alg->registered)
5272 crypto_unregister_aead(&t_alg->aead);
5273 }
5274
5275 for (i = 0; i < ARRAY_SIZE(driver_algs); i++) {

--- 108 unchanged lines hidden --- 		5273 for (i = 0; i < ARRAY_SIZE(driver_aeads); i++) {
5274 struct caam_aead_alg *t_alg = driver_aeads + i;
5275
5276 if (t_alg->registered)
5277 crypto_unregister_aead(&t_alg->aead);
5278 }
5279
5280 for (i = 0; i < ARRAY_SIZE(driver_algs); i++) {

--- 108 unchanged lines hidden ---