timer-riscv.c (3b5d1afd1f13bcab85eaa28223ad396694f929e3) timer-riscv.c (2bc3fc877aa9c4c8b80cc49f66dfcb7e4857a128)
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2012 Regents of the University of California
4 * Copyright (C) 2017 SiFive
5 *
6 * All RISC-V systems have a timer attached to every hart. These timers can
7 * either be read from the "time" and "timeh" CSRs, and can use the SBI to
8 * setup events, or directly accessed using MMIO registers.

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14#include <linux/irq.h>
15#include <linux/irqdomain.h>
16#include <linux/sched_clock.h>
17#include <linux/io-64-nonatomic-lo-hi.h>
18#include <linux/interrupt.h>
19#include <linux/of_irq.h>
20#include <asm/smp.h>
21#include <asm/sbi.h>
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2012 Regents of the University of California
4 * Copyright (C) 2017 SiFive
5 *
6 * All RISC-V systems have a timer attached to every hart. These timers can
7 * either be read from the "time" and "timeh" CSRs, and can use the SBI to
8 * setup events, or directly accessed using MMIO registers.

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14#include <linux/irq.h>
15#include <linux/irqdomain.h>
16#include <linux/sched_clock.h>
17#include <linux/io-64-nonatomic-lo-hi.h>
18#include <linux/interrupt.h>
19#include <linux/of_irq.h>
20#include <asm/smp.h>
21#include <asm/sbi.h>
22#include <asm/timex.h>
22
23
23u64 __iomem *riscv_time_cmp;
24u64 __iomem *riscv_time_val;
25
26static inline void mmio_set_timer(u64 val)
27{
28 void __iomem *r;
29
30 r = riscv_time_cmp + cpuid_to_hartid_map(smp_processor_id());
31 writeq_relaxed(val, r);
32}
33
34static int riscv_clock_next_event(unsigned long delta,
35 struct clock_event_device *ce)
36{
37 csr_set(CSR_IE, IE_TIE);
24static int riscv_clock_next_event(unsigned long delta,
25 struct clock_event_device *ce)
26{
27 csr_set(CSR_IE, IE_TIE);
38 if (IS_ENABLED(CONFIG_RISCV_SBI))
39 sbi_set_timer(get_cycles64() + delta);
40 else
41 mmio_set_timer(get_cycles64() + delta);
28 sbi_set_timer(get_cycles64() + delta);
42 return 0;
43}
44
45static unsigned int riscv_clock_event_irq;
46static DEFINE_PER_CPU(struct clock_event_device, riscv_clock_event) = {
47 .name = "riscv_timer_clockevent",
48 .features = CLOCK_EVT_FEAT_ONESHOT,
49 .rating = 100,

--- 126 unchanged lines hidden --- 		29 return 0;
30}
31
32static unsigned int riscv_clock_event_irq;
33static DEFINE_PER_CPU(struct clock_event_device, riscv_clock_event) = {
34 .name = "riscv_timer_clockevent",
35 .features = CLOCK_EVT_FEAT_ONESHOT,
36 .rating = 100,

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