timer-mediatek.c (4f2c0a4acffbec01079c28f839422e64ddeff004) timer-mediatek.c (49d576ea72a4fa5be15717babfa308b70b2bc5a4)
1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Mediatek SoCs General-Purpose Timer handling.
4 *
5 * Copyright (C) 2014 Matthias Brugger
6 *
7 * Matthias Brugger <matthias.bgg@gmail.com>
8 */

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17#include <linux/slab.h>
18#include "timer-of.h"
19
20#define TIMER_CLK_EVT (1)
21#define TIMER_CLK_SRC (2)
22
23#define TIMER_SYNC_TICKS (3)
24
1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Mediatek SoCs General-Purpose Timer handling.
4 *
5 * Copyright (C) 2014 Matthias Brugger
6 *
7 * Matthias Brugger <matthias.bgg@gmail.com>
8 */

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17#include <linux/slab.h>
18#include "timer-of.h"
19
20#define TIMER_CLK_EVT (1)
21#define TIMER_CLK_SRC (2)
22
23#define TIMER_SYNC_TICKS (3)
24
25/* cpux mcusys wrapper */
26#define CPUX_CON_REG 0x0
27#define CPUX_IDX_REG 0x4
28
29/* cpux */
30#define CPUX_IDX_GLOBAL_CTRL 0x0
31 #define CPUX_ENABLE BIT(0)
32 #define CPUX_CLK_DIV_MASK GENMASK(10, 8)
33 #define CPUX_CLK_DIV1 BIT(8)
34 #define CPUX_CLK_DIV2 BIT(9)
35 #define CPUX_CLK_DIV4 BIT(10)
36#define CPUX_IDX_GLOBAL_IRQ 0x30
37
38/* gpt */
39#define GPT_IRQ_EN_REG 0x00
40#define GPT_IRQ_ENABLE(val) BIT((val) - 1)
41#define GPT_IRQ_ACK_REG 0x08
42#define GPT_IRQ_ACK(val) BIT((val) - 1)
43
44#define GPT_CTRL_REG(val) (0x10 * (val))
45#define GPT_CTRL_OP(val) (((val) & 0x3) << 4)

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80 * SYST_CON_IRQ_CLR: Set to clear interrupt.
81 */
82#define SYST_CON_EN BIT(0)
83#define SYST_CON_IRQ_EN BIT(1)
84#define SYST_CON_IRQ_CLR BIT(4)
85
86static void __iomem *gpt_sched_reg __read_mostly;
87
25/* gpt */
26#define GPT_IRQ_EN_REG 0x00
27#define GPT_IRQ_ENABLE(val) BIT((val) - 1)
28#define GPT_IRQ_ACK_REG 0x08
29#define GPT_IRQ_ACK(val) BIT((val) - 1)
30
31#define GPT_CTRL_REG(val) (0x10 * (val))
32#define GPT_CTRL_OP(val) (((val) & 0x3) << 4)

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67 * SYST_CON_IRQ_CLR: Set to clear interrupt.
68 */
69#define SYST_CON_EN BIT(0)
70#define SYST_CON_IRQ_EN BIT(1)
71#define SYST_CON_IRQ_CLR BIT(4)
72
73static void __iomem *gpt_sched_reg __read_mostly;
74
88static u32 mtk_cpux_readl(u32 reg_idx, struct timer_of *to)
89{
90 writel(reg_idx, timer_of_base(to) + CPUX_IDX_REG);
91 return readl(timer_of_base(to) + CPUX_CON_REG);
92}
93
94static void mtk_cpux_writel(u32 val, u32 reg_idx, struct timer_of *to)
95{
96 writel(reg_idx, timer_of_base(to) + CPUX_IDX_REG);
97 writel(val, timer_of_base(to) + CPUX_CON_REG);
98}
99
100static void mtk_cpux_set_irq(struct timer_of *to, bool enable)
101{
102 const unsigned long *irq_mask = cpumask_bits(cpu_possible_mask);
103 u32 val;
104
105 val = mtk_cpux_readl(CPUX_IDX_GLOBAL_IRQ, to);
106
107 if (enable)
108 val |= *irq_mask;
109 else
110 val &= ~(*irq_mask);
111
112 mtk_cpux_writel(val, CPUX_IDX_GLOBAL_IRQ, to);
113}
114
115static int mtk_cpux_clkevt_shutdown(struct clock_event_device *clkevt)
116{
117 /* Clear any irq */
118 mtk_cpux_set_irq(to_timer_of(clkevt), false);
119
120 /*
121 * Disabling CPUXGPT timer will crash the platform, especially
122 * if Trusted Firmware is using it (usually, for sleep states),
123 * so we only mask the IRQ and call it a day.
124 */
125 return 0;
126}
127
128static int mtk_cpux_clkevt_resume(struct clock_event_device *clkevt)
129{
130 mtk_cpux_set_irq(to_timer_of(clkevt), true);
131 return 0;
132}
133
134static void mtk_syst_ack_irq(struct timer_of *to)
135{
136 /* Clear and disable interrupt */
137 writel(SYST_CON_EN, SYST_CON_REG(to));
138 writel(SYST_CON_IRQ_CLR | SYST_CON_EN, SYST_CON_REG(to));
139}
140
141static irqreturn_t mtk_syst_handler(int irq, void *dev_id)

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335 .cpumask = cpu_possible_mask,
336 },
337
338 .of_irq = {
339 .flags = IRQF_TIMER | IRQF_IRQPOLL,
340 },
341};
342
75static void mtk_syst_ack_irq(struct timer_of *to)
76{
77 /* Clear and disable interrupt */
78 writel(SYST_CON_EN, SYST_CON_REG(to));
79 writel(SYST_CON_IRQ_CLR | SYST_CON_EN, SYST_CON_REG(to));
80}
81
82static irqreturn_t mtk_syst_handler(int irq, void *dev_id)

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276 .cpumask = cpu_possible_mask,
277 },
278
279 .of_irq = {
280 .flags = IRQF_TIMER | IRQF_IRQPOLL,
281 },
282};
283
343static int __init mtk_cpux_init(struct device_node *node)
344{
345 static struct timer_of to_cpux;
346 u32 freq, val;
347 int ret;
348
349 /*
350 * There are per-cpu interrupts for the CPUX General Purpose Timer
351 * but since this timer feeds the AArch64 System Timer we can rely
352 * on the CPU timer PPIs as well, so we don't declare TIMER_OF_IRQ.
353 */
354 to_cpux.flags = TIMER_OF_BASE | TIMER_OF_CLOCK;
355 to_cpux.clkevt.name = "mtk-cpuxgpt";
356 to_cpux.clkevt.rating = 10;
357 to_cpux.clkevt.cpumask = cpu_possible_mask;
358 to_cpux.clkevt.set_state_shutdown = mtk_cpux_clkevt_shutdown;
359 to_cpux.clkevt.tick_resume = mtk_cpux_clkevt_resume;
360
361 /* If this fails, bad things are about to happen... */
362 ret = timer_of_init(node, &to_cpux);
363 if (ret) {
364 WARN(1, "Cannot start CPUX timers.\n");
365 return ret;
366 }
367
368 /*
369 * Check if we're given a clock with the right frequency for this
370 * timer, otherwise warn but keep going with the setup anyway, as
371 * that makes it possible to still boot the kernel, even though
372 * it may not work correctly (random lockups, etc).
373 * The reason behind this is that having an early UART may not be
374 * possible for everyone and this gives a chance to retrieve kmsg
375 * for eventual debugging even on consumer devices.
376 */
377 freq = timer_of_rate(&to_cpux);
378 if (freq > 13000000)
379 WARN(1, "Requested unsupported timer frequency %u\n", freq);
380
381 /* Clock input is 26MHz, set DIV2 to achieve 13MHz clock */
382 val = mtk_cpux_readl(CPUX_IDX_GLOBAL_CTRL, &to_cpux);
383 val &= ~CPUX_CLK_DIV_MASK;
384 val |= CPUX_CLK_DIV2;
385 mtk_cpux_writel(val, CPUX_IDX_GLOBAL_CTRL, &to_cpux);
386
387 /* Enable all CPUXGPT timers */
388 val = mtk_cpux_readl(CPUX_IDX_GLOBAL_CTRL, &to_cpux);
389 mtk_cpux_writel(val | CPUX_ENABLE, CPUX_IDX_GLOBAL_CTRL, &to_cpux);
390
391 clockevents_config_and_register(&to_cpux.clkevt, timer_of_rate(&to_cpux),
392 TIMER_SYNC_TICKS, 0xffffffff);
393
394 return 0;
395}
396
397static int __init mtk_syst_init(struct device_node *node)
398{
399 int ret;
400
401 to.clkevt.features = CLOCK_EVT_FEAT_DYNIRQ | CLOCK_EVT_FEAT_ONESHOT;
402 to.clkevt.set_state_shutdown = mtk_syst_clkevt_shutdown;
403 to.clkevt.set_state_oneshot = mtk_syst_clkevt_oneshot;
404 to.clkevt.tick_resume = mtk_syst_clkevt_resume;

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447 TIMER_SYNC_TICKS, 0xffffffff);
448
449 mtk_gpt_enable_irq(&to, TIMER_CLK_EVT);
450
451 return 0;
452}
453TIMER_OF_DECLARE(mtk_mt6577, "mediatek,mt6577-timer", mtk_gpt_init);
454TIMER_OF_DECLARE(mtk_mt6765, "mediatek,mt6765-timer", mtk_syst_init);
284static int __init mtk_syst_init(struct device_node *node)
285{
286 int ret;
287
288 to.clkevt.features = CLOCK_EVT_FEAT_DYNIRQ | CLOCK_EVT_FEAT_ONESHOT;
289 to.clkevt.set_state_shutdown = mtk_syst_clkevt_shutdown;
290 to.clkevt.set_state_oneshot = mtk_syst_clkevt_oneshot;
291 to.clkevt.tick_resume = mtk_syst_clkevt_resume;

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334 TIMER_SYNC_TICKS, 0xffffffff);
335
336 mtk_gpt_enable_irq(&to, TIMER_CLK_EVT);
337
338 return 0;
339}
340TIMER_OF_DECLARE(mtk_mt6577, "mediatek,mt6577-timer", mtk_gpt_init);
341TIMER_OF_DECLARE(mtk_mt6765, "mediatek,mt6765-timer", mtk_syst_init);
455TIMER_OF_DECLARE(mtk_mt6795, "mediatek,mt6795-systimer", mtk_cpux_init);