clksrc-dbx500-prcmu.c (b7d3622a39fde7658170b7f3cf6c6889bb8db30d) clksrc-dbx500-prcmu.c (9d2aa8c7961ae9af5f75af2dc171dd4e4f441e89)
1/*
2 * Copyright (C) ST-Ericsson SA 2011
3 *
4 * License Terms: GNU General Public License v2
5 * Author: Mattias Wallin <mattias.wallin@stericsson.com> for ST-Ericsson
6 * Author: Sundar Iyer for ST-Ericsson
7 * sched_clock implementation is based on:
8 * plat-nomadik/timer.c Linus Walleij <linus.walleij@stericsson.com>
9 *
10 * DBx500-PRCMU Timer
11 * The PRCMU has 5 timers which are available in a always-on
12 * power domain. We use the Timer 4 for our always-on clock
13 * source on DB8500.
14 */
1/*
2 * Copyright (C) ST-Ericsson SA 2011
3 *
4 * License Terms: GNU General Public License v2
5 * Author: Mattias Wallin <mattias.wallin@stericsson.com> for ST-Ericsson
6 * Author: Sundar Iyer for ST-Ericsson
7 * sched_clock implementation is based on:
8 * plat-nomadik/timer.c Linus Walleij <linus.walleij@stericsson.com>
9 *
10 * DBx500-PRCMU Timer
11 * The PRCMU has 5 timers which are available in a always-on
12 * power domain. We use the Timer 4 for our always-on clock
13 * source on DB8500.
14 */
15#include <linux/of.h>
16#include <linux/of_address.h>
15#include <linux/clockchips.h>
17#include <linux/clockchips.h>
16#include <linux/clksrc-dbx500-prcmu.h>
17#include <linux/sched_clock.h>
18
19#define RATE_32K 32768
20
21#define TIMER_MODE_CONTINOUS 0x1
22#define TIMER_DOWNCOUNT_VAL 0xffffffff
23
24#define PRCMU_TIMER_REF 0

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58 if (unlikely(!clksrc_dbx500_timer_base))
59 return 0;
60
61 return clksrc_dbx500_prcmu_read(&clocksource_dbx500_prcmu);
62}
63
64#endif
65
18#include <linux/sched_clock.h>
19
20#define RATE_32K 32768
21
22#define TIMER_MODE_CONTINOUS 0x1
23#define TIMER_DOWNCOUNT_VAL 0xffffffff
24
25#define PRCMU_TIMER_REF 0

--- 33 unchanged lines hidden (view full) ---

59 if (unlikely(!clksrc_dbx500_timer_base))
60 return 0;
61
62 return clksrc_dbx500_prcmu_read(&clocksource_dbx500_prcmu);
63}
64
65#endif
66
66void __init clksrc_dbx500_prcmu_init(void __iomem *base)
67static void __init clksrc_dbx500_prcmu_init(struct device_node *node)
67{
68{
68 clksrc_dbx500_timer_base = base;
69 clksrc_dbx500_timer_base = of_iomap(node, 0);
69
70 /*
71 * The A9 sub system expects the timer to be configured as
72 * a continous looping timer.
73 * The PRCMU should configure it but if it for some reason
74 * don't we do it here.
75 */
76 if (readl(clksrc_dbx500_timer_base + PRCMU_TIMER_MODE) !=
77 TIMER_MODE_CONTINOUS) {
78 writel(TIMER_MODE_CONTINOUS,
79 clksrc_dbx500_timer_base + PRCMU_TIMER_MODE);
80 writel(TIMER_DOWNCOUNT_VAL,
81 clksrc_dbx500_timer_base + PRCMU_TIMER_REF);
82 }
83#ifdef CONFIG_CLKSRC_DBX500_PRCMU_SCHED_CLOCK
84 sched_clock_register(dbx500_prcmu_sched_clock_read, 32, RATE_32K);
85#endif
86 clocksource_register_hz(&clocksource_dbx500_prcmu, RATE_32K);
87}
70
71 /*
72 * The A9 sub system expects the timer to be configured as
73 * a continous looping timer.
74 * The PRCMU should configure it but if it for some reason
75 * don't we do it here.
76 */
77 if (readl(clksrc_dbx500_timer_base + PRCMU_TIMER_MODE) !=
78 TIMER_MODE_CONTINOUS) {
79 writel(TIMER_MODE_CONTINOUS,
80 clksrc_dbx500_timer_base + PRCMU_TIMER_MODE);
81 writel(TIMER_DOWNCOUNT_VAL,
82 clksrc_dbx500_timer_base + PRCMU_TIMER_REF);
83 }
84#ifdef CONFIG_CLKSRC_DBX500_PRCMU_SCHED_CLOCK
85 sched_clock_register(dbx500_prcmu_sched_clock_read, 32, RATE_32K);
86#endif
87 clocksource_register_hz(&clocksource_dbx500_prcmu, RATE_32K);
88}
89CLOCKSOURCE_OF_DECLARE(dbx500_prcmu, "stericsson,db8500-prcmu-timer-4",
90 clksrc_dbx500_prcmu_init);