divider.c (fc9fb8fb985c092f9cf01c7c50269c132efc4d58) divider.c (0667a8d144bc830d0a752f079c9789735cd4f1f8)
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Zynq UltraScale+ MPSoC Divider support
4 *
5 * Copyright (C) 2016-2019 Xilinx
6 *
7 * Adjustable divider clock implementation
8 */

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78 unsigned long parent_rate)
79{
80 struct zynqmp_clk_divider *divider = to_zynqmp_clk_divider(hw);
81 const char *clk_name = clk_hw_get_name(hw);
82 u32 clk_id = divider->clk_id;
83 u32 div_type = divider->div_type;
84 u32 div, value;
85 int ret;
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Zynq UltraScale+ MPSoC Divider support
4 *
5 * Copyright (C) 2016-2019 Xilinx
6 *
7 * Adjustable divider clock implementation
8 */

--- 69 unchanged lines hidden (view full) ---

78 unsigned long parent_rate)
79{
80 struct zynqmp_clk_divider *divider = to_zynqmp_clk_divider(hw);
81 const char *clk_name = clk_hw_get_name(hw);
82 u32 clk_id = divider->clk_id;
83 u32 div_type = divider->div_type;
84 u32 div, value;
85 int ret;
86 const struct zynqmp_eemi_ops *eemi_ops = zynqmp_pm_get_eemi_ops();
87
86
88 ret = eemi_ops->clock_getdivider(clk_id, &div);
87 ret = zynqmp_pm_clock_getdivider(clk_id, &div);
89
90 if (ret)
91 pr_warn_once("%s() get divider failed for %s, ret = %d\n",
92 __func__, clk_name, ret);
93
94 if (div_type == TYPE_DIV1)
95 value = div & 0xFFFF;
96 else

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158 unsigned long *prate)
159{
160 struct zynqmp_clk_divider *divider = to_zynqmp_clk_divider(hw);
161 const char *clk_name = clk_hw_get_name(hw);
162 u32 clk_id = divider->clk_id;
163 u32 div_type = divider->div_type;
164 u32 bestdiv;
165 int ret;
88
89 if (ret)
90 pr_warn_once("%s() get divider failed for %s, ret = %d\n",
91 __func__, clk_name, ret);
92
93 if (div_type == TYPE_DIV1)
94 value = div & 0xFFFF;
95 else

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157 unsigned long *prate)
158{
159 struct zynqmp_clk_divider *divider = to_zynqmp_clk_divider(hw);
160 const char *clk_name = clk_hw_get_name(hw);
161 u32 clk_id = divider->clk_id;
162 u32 div_type = divider->div_type;
163 u32 bestdiv;
164 int ret;
166 const struct zynqmp_eemi_ops *eemi_ops = zynqmp_pm_get_eemi_ops();
167
168 /* if read only, just return current value */
169 if (divider->flags & CLK_DIVIDER_READ_ONLY) {
165
166 /* if read only, just return current value */
167 if (divider->flags & CLK_DIVIDER_READ_ONLY) {
170 ret = eemi_ops->clock_getdivider(clk_id, &bestdiv);
168 ret = zynqmp_pm_clock_getdivider(clk_id, &bestdiv);
171
172 if (ret)
173 pr_warn_once("%s() get divider failed for %s, ret = %d\n",
174 __func__, clk_name, ret);
175 if (div_type == TYPE_DIV1)
176 bestdiv = bestdiv & 0xFFFF;
177 else
178 bestdiv = bestdiv >> 16;

--- 154 unchanged lines hidden --- 		169
170 if (ret)
171 pr_warn_once("%s() get divider failed for %s, ret = %d\n",
172 __func__, clk_name, ret);
173 if (div_type == TYPE_DIV1)
174 bestdiv = bestdiv & 0xFFFF;
175 else
176 bestdiv = bestdiv >> 16;

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