divider.c (2ce7e495dab4647055f6cf300bc66870dc8a7cab) divider.c (9d66e85784f196fb7442193a1d7f3896ed418806)
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Zynq UltraScale+ MPSoC Divider support
4 *
5 * Copyright (C) 2016-2019 Xilinx
6 *
7 * Adjustable divider clock implementation
8 */

--- 252 unchanged lines hidden (view full) ---

261/**
262 * zynqmp_clk_get_max_divisor() - Get maximum supported divisor from firmware.
263 * @clk_id: Id of clock
264 * @type: Divider type
265 *
266 * Return: Maximum divisor of a clock if query data is successful
267 * U16_MAX in case of query data is not success
268 */
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Zynq UltraScale+ MPSoC Divider support
4 *
5 * Copyright (C) 2016-2019 Xilinx
6 *
7 * Adjustable divider clock implementation
8 */

--- 252 unchanged lines hidden (view full) ---

261/**
262 * zynqmp_clk_get_max_divisor() - Get maximum supported divisor from firmware.
263 * @clk_id: Id of clock
264 * @type: Divider type
265 *
266 * Return: Maximum divisor of a clock if query data is successful
267 * U16_MAX in case of query data is not success
268 */
269u32 zynqmp_clk_get_max_divisor(u32 clk_id, u32 type)
269static u32 zynqmp_clk_get_max_divisor(u32 clk_id, u32 type)
270{
271 const struct zynqmp_eemi_ops *eemi_ops = zynqmp_pm_get_eemi_ops();
272 struct zynqmp_pm_query_data qdata = {0};
273 u32 ret_payload[PAYLOAD_ARG_CNT];
274 int ret;
275
276 qdata.qid = PM_QID_CLOCK_GET_MAX_DIVISOR;
277 qdata.arg1 = clk_id;

--- 68 unchanged lines hidden --- 		270{
271 const struct zynqmp_eemi_ops *eemi_ops = zynqmp_pm_get_eemi_ops();
272 struct zynqmp_pm_query_data qdata = {0};
273 u32 ret_payload[PAYLOAD_ARG_CNT];
274 int ret;
275
276 qdata.qid = PM_QID_CLOCK_GET_MAX_DIVISOR;
277 qdata.arg1 = clk_id;

--- 68 unchanged lines hidden ---