clk-zynqmp.h (610a5d83010eaf02a857321092cf0cd02178bee7) clk-zynqmp.h (1b09c308e64969f545f4b9474b786ad90dddf9a2)
1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Copyright (C) 2016-2018 Xilinx
4 */
5
6#ifndef __LINUX_CLK_ZYNQMP_H_
7#define __LINUX_CLK_ZYNQMP_H_
8

--- 10 unchanged lines hidden (view full) ---

19#define ZYNQMP_CLK_SET_RATE_PARENT BIT(2)
20/* do not gate even if unused */
21#define ZYNQMP_CLK_IGNORE_UNUSED BIT(3)
22/* don't re-parent on rate change */
23#define ZYNQMP_CLK_SET_RATE_NO_REPARENT BIT(7)
24/* do not gate, ever */
25#define ZYNQMP_CLK_IS_CRITICAL BIT(11)
26
1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Copyright (C) 2016-2018 Xilinx
4 */
5
6#ifndef __LINUX_CLK_ZYNQMP_H_
7#define __LINUX_CLK_ZYNQMP_H_
8

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19#define ZYNQMP_CLK_SET_RATE_PARENT BIT(2)
20/* do not gate even if unused */
21#define ZYNQMP_CLK_IGNORE_UNUSED BIT(3)
22/* don't re-parent on rate change */
23#define ZYNQMP_CLK_SET_RATE_NO_REPARENT BIT(7)
24/* do not gate, ever */
25#define ZYNQMP_CLK_IS_CRITICAL BIT(11)
26
27/* Type Flags for divider clock */
28#define ZYNQMP_CLK_DIVIDER_ONE_BASED BIT(0)
29#define ZYNQMP_CLK_DIVIDER_POWER_OF_TWO BIT(1)
30#define ZYNQMP_CLK_DIVIDER_ALLOW_ZERO BIT(2)
31#define ZYNQMP_CLK_DIVIDER_HIWORD_MASK BIT(3)
32#define ZYNQMP_CLK_DIVIDER_ROUND_CLOSEST BIT(4)
33#define ZYNQMP_CLK_DIVIDER_READ_ONLY BIT(5)
34#define ZYNQMP_CLK_DIVIDER_MAX_AT_ZERO BIT(6)
35
27enum topology_type {
28 TYPE_INVALID,
29 TYPE_MUX,
30 TYPE_PLL,
31 TYPE_FIXEDFACTOR,
32 TYPE_DIV1,
33 TYPE_DIV2,
34 TYPE_GATE,

--- 45 unchanged lines hidden --- 		36enum topology_type {
37 TYPE_INVALID,
38 TYPE_MUX,
39 TYPE_PLL,
40 TYPE_FIXEDFACTOR,
41 TYPE_DIV1,
42 TYPE_DIV2,
43 TYPE_GATE,

--- 45 unchanged lines hidden ---