clkc.c (e8e6e6012d68c4967e8f26fdd39ac95c247d4789) clkc.c (4a32c74e762236a53627536b9b9c1693d3073359)
1/*
2 * Zynq clock controller
3 *
4 * Copyright (C) 2012 - 2013 Xilinx
5 *
6 * Sören Brinkmann <soren.brinkmann@xilinx.com>
7 *
8 * This program is free software: you can redistribute it and/or modify

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16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program. If not, see <http://www.gnu.org/licenses/>.
19 */
20
21#include <linux/clk/zynq.h>
22#include <linux/clk-provider.h>
23#include <linux/of.h>
1/*
2 * Zynq clock controller
3 *
4 * Copyright (C) 2012 - 2013 Xilinx
5 *
6 * Sören Brinkmann <soren.brinkmann@xilinx.com>
7 *
8 * This program is free software: you can redistribute it and/or modify

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16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program. If not, see <http://www.gnu.org/licenses/>.
19 */
20
21#include <linux/clk/zynq.h>
22#include <linux/clk-provider.h>
23#include <linux/of.h>
24#include <linux/of_address.h>
24#include <linux/slab.h>
25#include <linux/string.h>
26#include <linux/io.h>
27
25#include <linux/slab.h>
26#include <linux/string.h>
27#include <linux/io.h>
28
28static void __iomem *zynq_slcr_base_priv;
29static void __iomem *zynq_clkc_base;
29
30
30#define SLCR_ARMPLL_CTRL (zynq_slcr_base_priv + 0x100)
31#define SLCR_DDRPLL_CTRL (zynq_slcr_base_priv + 0x104)
32#define SLCR_IOPLL_CTRL (zynq_slcr_base_priv + 0x108)
33#define SLCR_PLL_STATUS (zynq_slcr_base_priv + 0x10c)
34#define SLCR_ARM_CLK_CTRL (zynq_slcr_base_priv + 0x120)
35#define SLCR_DDR_CLK_CTRL (zynq_slcr_base_priv + 0x124)
36#define SLCR_DCI_CLK_CTRL (zynq_slcr_base_priv + 0x128)
37#define SLCR_APER_CLK_CTRL (zynq_slcr_base_priv + 0x12c)
38#define SLCR_GEM0_CLK_CTRL (zynq_slcr_base_priv + 0x140)
39#define SLCR_GEM1_CLK_CTRL (zynq_slcr_base_priv + 0x144)
40#define SLCR_SMC_CLK_CTRL (zynq_slcr_base_priv + 0x148)
41#define SLCR_LQSPI_CLK_CTRL (zynq_slcr_base_priv + 0x14c)
42#define SLCR_SDIO_CLK_CTRL (zynq_slcr_base_priv + 0x150)
43#define SLCR_UART_CLK_CTRL (zynq_slcr_base_priv + 0x154)
44#define SLCR_SPI_CLK_CTRL (zynq_slcr_base_priv + 0x158)
45#define SLCR_CAN_CLK_CTRL (zynq_slcr_base_priv + 0x15c)
46#define SLCR_CAN_MIOCLK_CTRL (zynq_slcr_base_priv + 0x160)
47#define SLCR_DBG_CLK_CTRL (zynq_slcr_base_priv + 0x164)
48#define SLCR_PCAP_CLK_CTRL (zynq_slcr_base_priv + 0x168)
49#define SLCR_FPGA0_CLK_CTRL (zynq_slcr_base_priv + 0x170)
50#define SLCR_621_TRUE (zynq_slcr_base_priv + 0x1c4)
51#define SLCR_SWDT_CLK_SEL (zynq_slcr_base_priv + 0x304)
31#define SLCR_ARMPLL_CTRL (zynq_clkc_base + 0x00)
32#define SLCR_DDRPLL_CTRL (zynq_clkc_base + 0x04)
33#define SLCR_IOPLL_CTRL (zynq_clkc_base + 0x08)
34#define SLCR_PLL_STATUS (zynq_clkc_base + 0x0c)
35#define SLCR_ARM_CLK_CTRL (zynq_clkc_base + 0x20)
36#define SLCR_DDR_CLK_CTRL (zynq_clkc_base + 0x24)
37#define SLCR_DCI_CLK_CTRL (zynq_clkc_base + 0x28)
38#define SLCR_APER_CLK_CTRL (zynq_clkc_base + 0x2c)
39#define SLCR_GEM0_CLK_CTRL (zynq_clkc_base + 0x40)
40#define SLCR_GEM1_CLK_CTRL (zynq_clkc_base + 0x44)
41#define SLCR_SMC_CLK_CTRL (zynq_clkc_base + 0x48)
42#define SLCR_LQSPI_CLK_CTRL (zynq_clkc_base + 0x4c)
43#define SLCR_SDIO_CLK_CTRL (zynq_clkc_base + 0x50)
44#define SLCR_UART_CLK_CTRL (zynq_clkc_base + 0x54)
45#define SLCR_SPI_CLK_CTRL (zynq_clkc_base + 0x58)
46#define SLCR_CAN_CLK_CTRL (zynq_clkc_base + 0x5c)
47#define SLCR_CAN_MIOCLK_CTRL (zynq_clkc_base + 0x60)
48#define SLCR_DBG_CLK_CTRL (zynq_clkc_base + 0x64)
49#define SLCR_PCAP_CLK_CTRL (zynq_clkc_base + 0x68)
50#define SLCR_FPGA0_CLK_CTRL (zynq_clkc_base + 0x70)
51#define SLCR_621_TRUE (zynq_clkc_base + 0xc4)
52#define SLCR_SWDT_CLK_SEL (zynq_clkc_base + 0x204)
52
53#define NUM_MIO_PINS 54
54
55enum zynq_clk {
56 armpll, ddrpll, iopll,
57 cpu_6or4x, cpu_3or2x, cpu_2x, cpu_1x,
58 ddr2x, ddr3x, dci,
59 lqspi, smc, pcap, gem0, gem1, fclk0, fclk1, fclk2, fclk3, can0, can1,

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564
565 clk_data.clks = clks;
566 clk_data.clk_num = ARRAY_SIZE(clks);
567 of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
568}
569
570CLK_OF_DECLARE(zynq_clkc, "xlnx,ps7-clkc", zynq_clk_setup);
571
53
54#define NUM_MIO_PINS 54
55
56enum zynq_clk {
57 armpll, ddrpll, iopll,
58 cpu_6or4x, cpu_3or2x, cpu_2x, cpu_1x,
59 ddr2x, ddr3x, dci,
60 lqspi, smc, pcap, gem0, gem1, fclk0, fclk1, fclk2, fclk3, can0, can1,

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565
566 clk_data.clks = clks;
567 clk_data.clk_num = ARRAY_SIZE(clks);
568 of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
569}
570
571CLK_OF_DECLARE(zynq_clkc, "xlnx,ps7-clkc", zynq_clk_setup);
572
572void __init zynq_clock_init(void __iomem *slcr_base)
573void __init zynq_clock_init(void)
573{
574{
574 zynq_slcr_base_priv = slcr_base;
575 of_clk_init(NULL);
575 struct device_node *np;
576 struct device_node *slcr;
577 struct resource res;
578
579 np = of_find_compatible_node(NULL, NULL, "xlnx,ps7-clkc");
580 if (!np) {
581 pr_err("%s: clkc node not found\n", __func__);
582 goto np_err;
583 }
584
585 if (of_address_to_resource(np, 0, &res)) {
586 pr_err("%s: failed to get resource\n", np->name);
587 goto np_err;
588 }
589
590 slcr = of_get_parent(np);
591
592 if (slcr->data) {
593 zynq_clkc_base = (__force void __iomem *)slcr->data + res.start;
594 } else {
595 pr_err("%s: Unable to get I/O memory\n", np->name);
596 of_node_put(slcr);
597 goto np_err;
598 }
599
600 pr_info("%s: clkc starts at %p\n", __func__, zynq_clkc_base);
601
602 of_node_put(slcr);
603 of_node_put(np);
604
605 return;
606
607np_err:
608 of_node_put(np);
609 BUG();
610 return;
576}
611}