clk-lgm.c (4b4193256c8d3bc3a5397b5cd9494c2ad386317d) clk-lgm.c (036177310bac5534de44ff6a7b60a4d2c0b6567c)
1// SPDX-License-Identifier: GPL-2.0
2/*
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2020-2022 MaxLinear, Inc.
3 * Copyright (C) 2020 Intel Corporation.
4 * Copyright (C) 2020 Intel Corporation.
4 * Zhu YiXin <yixin.zhu@intel.com>
5 * Rahul Tanwar <rahul.tanwar@intel.com>
5 * Zhu Yixin <yzhu@maxlinear.com>
6 * Rahul Tanwar <rtanwar@maxlinear.com>
6 */
7#include <linux/clk-provider.h>
7 */
8#include <linux/clk-provider.h>
9#include <linux/mfd/syscon.h>
8#include <linux/of.h>
9#include <linux/platform_device.h>
10#include <dt-bindings/clock/intel,lgm-clk.h>
11#include "clk-cgu.h"
12
13#define PLL_DIV_WIDTH 4
14#define PLL_DDIV_WIDTH 3
15

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428
429 ctx = devm_kzalloc(dev, struct_size(ctx, clk_data.hws, CLK_NR_CLKS),
430 GFP_KERNEL);
431 if (!ctx)
432 return -ENOMEM;
433
434 ctx->clk_data.num = CLK_NR_CLKS;
435
10#include <linux/of.h>
11#include <linux/platform_device.h>
12#include <dt-bindings/clock/intel,lgm-clk.h>
13#include "clk-cgu.h"
14
15#define PLL_DIV_WIDTH 4
16#define PLL_DDIV_WIDTH 3
17

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430
431 ctx = devm_kzalloc(dev, struct_size(ctx, clk_data.hws, CLK_NR_CLKS),
432 GFP_KERNEL);
433 if (!ctx)
434 return -ENOMEM;
435
436 ctx->clk_data.num = CLK_NR_CLKS;
437
436 ctx->membase = devm_platform_ioremap_resource(pdev, 0);
437 if (IS_ERR(ctx->membase))
438 ctx->membase = syscon_node_to_regmap(np);
439 if (IS_ERR_OR_NULL(ctx->membase)) {
440 dev_err(dev, "Failed to get clk CGU iomem\n");
438 return PTR_ERR(ctx->membase);
441 return PTR_ERR(ctx->membase);
442 }
439
443
444
440 ctx->np = np;
441 ctx->dev = dev;
442 spin_lock_init(&ctx->lock);
443
444 ret = lgm_clk_register_plls(ctx, lgm_pll_clks,
445 ARRAY_SIZE(lgm_pll_clks));
446 if (ret)
447 return ret;

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445 ctx->np = np;
446 ctx->dev = dev;
447 spin_lock_init(&ctx->lock);
448
449 ret = lgm_clk_register_plls(ctx, lgm_pll_clks,
450 ARRAY_SIZE(lgm_pll_clks));
451 if (ret)
452 return ret;

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