clk-cgu.h (4b4193256c8d3bc3a5397b5cd9494c2ad386317d) clk-cgu.h (036177310bac5534de44ff6a7b60a4d2c0b6567c)
1/* SPDX-License-Identifier: GPL-2.0 */
2/*
1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Copyright(c) 2020 Intel Corporation.
4 * Zhu YiXin <yixin.zhu@intel.com>
5 * Rahul Tanwar <rahul.tanwar@intel.com>
3 * Copyright (C) 2020-2022 MaxLinear, Inc.
4 * Copyright (C) 2020 Intel Corporation.
5 * Zhu Yixin <yzhu@maxlinear.com>
6 * Rahul Tanwar <rtanwar@maxlinear.com>
6 */
7
8#ifndef __CLK_CGU_H
9#define __CLK_CGU_H
10
7 */
8
9#ifndef __CLK_CGU_H
10#define __CLK_CGU_H
11
11#include <linux/io.h>
12#include <linux/regmap.h>
12
13struct lgm_clk_mux {
14 struct clk_hw hw;
13
14struct lgm_clk_mux {
15 struct clk_hw hw;
15 void __iomem *membase;
16 struct regmap *membase;
16 unsigned int reg;
17 u8 shift;
18 u8 width;
19 unsigned long flags;
20 spinlock_t lock;
21};
22
23struct lgm_clk_divider {
24 struct clk_hw hw;
17 unsigned int reg;
18 u8 shift;
19 u8 width;
20 unsigned long flags;
21 spinlock_t lock;
22};
23
24struct lgm_clk_divider {
25 struct clk_hw hw;
25 void __iomem *membase;
26 struct regmap *membase;
26 unsigned int reg;
27 u8 shift;
28 u8 width;
29 u8 shift_gate;
30 u8 width_gate;
31 unsigned long flags;
32 const struct clk_div_table *table;
33 spinlock_t lock;
34};
35
36struct lgm_clk_ddiv {
37 struct clk_hw hw;
27 unsigned int reg;
28 u8 shift;
29 u8 width;
30 u8 shift_gate;
31 u8 width_gate;
32 unsigned long flags;
33 const struct clk_div_table *table;
34 spinlock_t lock;
35};
36
37struct lgm_clk_ddiv {
38 struct clk_hw hw;
38 void __iomem *membase;
39 struct regmap *membase;
39 unsigned int reg;
40 u8 shift0;
41 u8 width0;
42 u8 shift1;
43 u8 width1;
44 u8 shift2;
45 u8 width2;
46 u8 shift_gate;
47 u8 width_gate;
48 unsigned int mult;
49 unsigned int div;
50 unsigned long flags;
51 spinlock_t lock;
52};
53
54struct lgm_clk_gate {
55 struct clk_hw hw;
40 unsigned int reg;
41 u8 shift0;
42 u8 width0;
43 u8 shift1;
44 u8 width1;
45 u8 shift2;
46 u8 width2;
47 u8 shift_gate;
48 u8 width_gate;
49 unsigned int mult;
50 unsigned int div;
51 unsigned long flags;
52 spinlock_t lock;
53};
54
55struct lgm_clk_gate {
56 struct clk_hw hw;
56 void __iomem *membase;
57 struct regmap *membase;
57 unsigned int reg;
58 u8 shift;
59 unsigned long flags;
60 spinlock_t lock;
61};
62
63enum lgm_clk_type {
64 CLK_TYPE_FIXED,

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72/**
73 * struct lgm_clk_provider
74 * @membase: IO mem base address for CGU.
75 * @np: device node
76 * @dev: device
77 * @clk_data: array of hw clocks and clk number.
78 */
79struct lgm_clk_provider {
58 unsigned int reg;
59 u8 shift;
60 unsigned long flags;
61 spinlock_t lock;
62};
63
64enum lgm_clk_type {
65 CLK_TYPE_FIXED,

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73/**
74 * struct lgm_clk_provider
75 * @membase: IO mem base address for CGU.
76 * @np: device node
77 * @dev: device
78 * @clk_data: array of hw clocks and clk number.
79 */
80struct lgm_clk_provider {
80 void __iomem *membase;
81 struct regmap *membase;
81 struct device_node *np;
82 struct device *dev;
83 struct clk_hw_onecell_data clk_data;
84 spinlock_t lock;
85};
86
87enum pll_type {
88 TYPE_ROPLL,
89 TYPE_LJPLL,
90 TYPE_NONE,
91};
92
93struct lgm_clk_pll {
94 struct clk_hw hw;
82 struct device_node *np;
83 struct device *dev;
84 struct clk_hw_onecell_data clk_data;
85 spinlock_t lock;
86};
87
88enum pll_type {
89 TYPE_ROPLL,
90 TYPE_LJPLL,
91 TYPE_NONE,
92};
93
94struct lgm_clk_pll {
95 struct clk_hw hw;
95 void __iomem *membase;
96 struct regmap *membase;
96 unsigned int reg;
97 unsigned long flags;
98 enum pll_type type;
99 spinlock_t lock;
100};
101
102/**
103 * struct lgm_pll_clk_data

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295 .div_shift = _shift, \
296 .div_width = _width, \
297 .div_flags = _cf, \
298 .div_val = _v, \
299 .mult = _m, \
300 .div = _d, \
301 }
302
97 unsigned int reg;
98 unsigned long flags;
99 enum pll_type type;
100 spinlock_t lock;
101};
102
103/**
104 * struct lgm_pll_clk_data

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296 .div_shift = _shift, \
297 .div_width = _width, \
298 .div_flags = _cf, \
299 .div_val = _v, \
300 .mult = _m, \
301 .div = _d, \
302 }
303
303static inline void lgm_set_clk_val(void __iomem *membase, u32 reg,
304static inline void lgm_set_clk_val(struct regmap *membase, u32 reg,
304 u8 shift, u8 width, u32 set_val)
305{
306 u32 mask = (GENMASK(width - 1, 0) << shift);
305 u8 shift, u8 width, u32 set_val)
306{
307 u32 mask = (GENMASK(width - 1, 0) << shift);
307 u32 regval;
308
308
309 regval = readl(membase + reg);
310 regval = (regval & ~mask) | ((set_val << shift) & mask);
311 writel(regval, membase + reg);
309 regmap_update_bits(membase, reg, mask, set_val << shift);
312}
313
310}
311
314static inline u32 lgm_get_clk_val(void __iomem *membase, u32 reg,
312static inline u32 lgm_get_clk_val(struct regmap *membase, u32 reg,
315 u8 shift, u8 width)
316{
317 u32 mask = (GENMASK(width - 1, 0) << shift);
318 u32 val;
319
313 u8 shift, u8 width)
314{
315 u32 mask = (GENMASK(width - 1, 0) << shift);
316 u32 val;
317
320 val = readl(membase + reg);
318 if (regmap_read(membase, reg, &val)) {
319 WARN_ONCE(1, "Failed to read clk reg: 0x%x\n", reg);
320 return 0;
321 }
322
321 val = (val & mask) >> shift;
322
323 return val;
324}
325
323 val = (val & mask) >> shift;
324
325 return val;
326}
327
328
329
326int lgm_clk_register_branches(struct lgm_clk_provider *ctx,
327 const struct lgm_clk_branch *list,
328 unsigned int nr_clk);
329int lgm_clk_register_plls(struct lgm_clk_provider *ctx,
330 const struct lgm_pll_clk_data *list,
331 unsigned int nr_clk);
332int lgm_clk_register_ddiv(struct lgm_clk_provider *ctx,
333 const struct lgm_clk_ddiv_data *list,
334 unsigned int nr_clk);
335#endif /* __CLK_CGU_H */
330int lgm_clk_register_branches(struct lgm_clk_provider *ctx,
331 const struct lgm_clk_branch *list,
332 unsigned int nr_clk);
333int lgm_clk_register_plls(struct lgm_clk_provider *ctx,
334 const struct lgm_pll_clk_data *list,
335 unsigned int nr_clk);
336int lgm_clk_register_ddiv(struct lgm_clk_provider *ctx,
337 const struct lgm_clk_ddiv_data *list,
338 unsigned int nr_clk);
339#endif /* __CLK_CGU_H */