| clock.h (59245ce01a2e3ded836172266e3ac2e576a03333) | clock.h (ef14db0977547b1982d4f6eaa305e1a22eb95778) |
|---|---|
| 1/* 2 * TI Clock driver internal definitions 3 * 4 * Copyright (C) 2014 Texas Instruments, Inc 5 * Tero Kristo (t-kristo@ti.com) 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as --- 156 unchanged lines hidden (view full) --- 165struct clk_hw *ti_clk_build_component_gate(struct ti_clk_gate *setup); 166struct clk_hw *ti_clk_build_component_mux(struct ti_clk_mux *setup); 167 168void ti_clk_patch_legacy_clks(struct ti_clk **patch); 169struct clk *ti_clk_register_clk(struct ti_clk *setup); 170int ti_clk_register_legacy_clks(struct ti_clk_alias *clks); 171 172extern const struct clk_hw_omap_ops clkhwops_omap4_dpllmx; | 1/* 2 * TI Clock driver internal definitions 3 * 4 * Copyright (C) 2014 Texas Instruments, Inc 5 * Tero Kristo (t-kristo@ti.com) 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as --- 156 unchanged lines hidden (view full) --- 165struct clk_hw *ti_clk_build_component_gate(struct ti_clk_gate *setup); 166struct clk_hw *ti_clk_build_component_mux(struct ti_clk_mux *setup); 167 168void ti_clk_patch_legacy_clks(struct ti_clk **patch); 169struct clk *ti_clk_register_clk(struct ti_clk *setup); 170int ti_clk_register_legacy_clks(struct ti_clk_alias *clks); 171 172extern const struct clk_hw_omap_ops clkhwops_omap4_dpllmx; |
| 173extern const struct clk_hw_omap_ops clkhwops_iclk; 174extern const struct clk_hw_omap_ops clkhwops_iclk_wait; |
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| 173 174u8 omap2_init_dpll_parent(struct clk_hw *hw); 175 176unsigned long omap4_dpll_regm4xen_recalc(struct clk_hw *hw, 177 unsigned long parent_rate); 178long omap4_dpll_regm4xen_round_rate(struct clk_hw *hw, 179 unsigned long target_rate, 180 unsigned long *parent_rate); 181long omap4_dpll_regm4xen_determine_rate(struct clk_hw *hw, 182 unsigned long rate, 183 unsigned long min_rate, 184 unsigned long max_rate, 185 unsigned long *best_parent_rate, 186 struct clk_hw **best_parent_clk); 187 188#endif | 175 176u8 omap2_init_dpll_parent(struct clk_hw *hw); 177 178unsigned long omap4_dpll_regm4xen_recalc(struct clk_hw *hw, 179 unsigned long parent_rate); 180long omap4_dpll_regm4xen_round_rate(struct clk_hw *hw, 181 unsigned long target_rate, 182 unsigned long *parent_rate); 183long omap4_dpll_regm4xen_determine_rate(struct clk_hw *hw, 184 unsigned long rate, 185 unsigned long min_rate, 186 unsigned long max_rate, 187 unsigned long *best_parent_rate, 188 struct clk_hw **best_parent_clk); 189 190#endif |