clk-3xxx.c (f01387d2693813eb5271a3448e6a082322c7d75d) clk-3xxx.c (1a34275d347fd4602443417d11031b77d368cae9)
1/*
2 * OMAP3 Clock init
3 *
4 * Copyright (C) 2013 Texas Instruments, Inc
5 * Tero Kristo (t-kristo@ti.com)
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as

--- 313 unchanged lines hidden (view full) ---

322 "omapctrl_ick",
323};
324
325enum {
326 OMAP3_SOC_AM35XX,
327 OMAP3_SOC_OMAP3430_ES1,
328 OMAP3_SOC_OMAP3430_ES2_PLUS,
329 OMAP3_SOC_OMAP3630,
1/*
2 * OMAP3 Clock init
3 *
4 * Copyright (C) 2013 Texas Instruments, Inc
5 * Tero Kristo (t-kristo@ti.com)
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as

--- 313 unchanged lines hidden (view full) ---

322 "omapctrl_ick",
323};
324
325enum {
326 OMAP3_SOC_AM35XX,
327 OMAP3_SOC_OMAP3430_ES1,
328 OMAP3_SOC_OMAP3430_ES2_PLUS,
329 OMAP3_SOC_OMAP3630,
330 OMAP3_SOC_TI81XX,
331};
332
333static int __init omap3xxx_dt_clk_init(int soc_type)
334{
335 if (soc_type == OMAP3_SOC_AM35XX || soc_type == OMAP3_SOC_OMAP3630 ||
336 soc_type == OMAP3_SOC_OMAP3430_ES1 ||
337 soc_type == OMAP3_SOC_OMAP3430_ES2_PLUS)
338 ti_dt_clocks_register(omap3xxx_clks);

--- 26 unchanged lines hidden (view full) ---

365 ARRAY_SIZE(enable_init_clks));
366
367 pr_info("Clocking rate (Crystal/Core/MPU): %ld.%01ld/%ld/%ld MHz\n",
368 (clk_get_rate(clk_get_sys(NULL, "osc_sys_ck")) / 1000000),
369 (clk_get_rate(clk_get_sys(NULL, "osc_sys_ck")) / 100000) % 10,
370 (clk_get_rate(clk_get_sys(NULL, "core_ck")) / 1000000),
371 (clk_get_rate(clk_get_sys(NULL, "arm_fck")) / 1000000));
372
330};
331
332static int __init omap3xxx_dt_clk_init(int soc_type)
333{
334 if (soc_type == OMAP3_SOC_AM35XX || soc_type == OMAP3_SOC_OMAP3630 ||
335 soc_type == OMAP3_SOC_OMAP3430_ES1 ||
336 soc_type == OMAP3_SOC_OMAP3430_ES2_PLUS)
337 ti_dt_clocks_register(omap3xxx_clks);

--- 26 unchanged lines hidden (view full) ---

364 ARRAY_SIZE(enable_init_clks));
365
366 pr_info("Clocking rate (Crystal/Core/MPU): %ld.%01ld/%ld/%ld MHz\n",
367 (clk_get_rate(clk_get_sys(NULL, "osc_sys_ck")) / 1000000),
368 (clk_get_rate(clk_get_sys(NULL, "osc_sys_ck")) / 100000) % 10,
369 (clk_get_rate(clk_get_sys(NULL, "core_ck")) / 1000000),
370 (clk_get_rate(clk_get_sys(NULL, "arm_fck")) / 1000000));
371
373 if (soc_type != OMAP3_SOC_TI81XX && soc_type != OMAP3_SOC_OMAP3430_ES1)
372 if (soc_type != OMAP3_SOC_OMAP3430_ES1)
374 omap3_clk_lock_dpll5();
375
376 return 0;
377}
378
379int __init omap3430_dt_clk_init(void)
380{
381 return omap3xxx_dt_clk_init(OMAP3_SOC_OMAP3430_ES2_PLUS);
382}
383
384int __init omap3630_dt_clk_init(void)
385{
386 return omap3xxx_dt_clk_init(OMAP3_SOC_OMAP3630);
387}
388
389int __init am35xx_dt_clk_init(void)
390{
391 return omap3xxx_dt_clk_init(OMAP3_SOC_AM35XX);
392}
373 omap3_clk_lock_dpll5();
374
375 return 0;
376}
377
378int __init omap3430_dt_clk_init(void)
379{
380 return omap3xxx_dt_clk_init(OMAP3_SOC_OMAP3430_ES2_PLUS);
381}
382
383int __init omap3630_dt_clk_init(void)
384{
385 return omap3xxx_dt_clk_init(OMAP3_SOC_OMAP3630);
386}
387
388int __init am35xx_dt_clk_init(void)
389{
390 return omap3xxx_dt_clk_init(OMAP3_SOC_AM35XX);
391}
393
394int __init ti81xx_dt_clk_init(void)
395{
396 return omap3xxx_dt_clk_init(OMAP3_SOC_TI81XX);
397}