clk-tegra30.c (ff36e78fdb251b9fa65028554689806961e011eb) clk-tegra30.c (9a85eb4d62425555ccdc774d906e6bbca5ffccc0)
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
4 */
5
6#include <linux/io.h>
7#include <linux/delay.h>
8#include <linux/clk-provider.h>

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578 { .con_id = "sclk", .dt_id = TEGRA30_CLK_SCLK },
579 { .con_id = "hclk", .dt_id = TEGRA30_CLK_HCLK },
580 { .con_id = "pclk", .dt_id = TEGRA30_CLK_PCLK },
581 { .con_id = "twd", .dt_id = TEGRA30_CLK_TWD },
582 { .con_id = "emc", .dt_id = TEGRA30_CLK_EMC },
583 { .con_id = "clk_32k", .dt_id = TEGRA30_CLK_CLK_32K },
584 { .con_id = "clk_m_div2", .dt_id = TEGRA30_CLK_CLK_M_DIV2 },
585 { .con_id = "clk_m_div4", .dt_id = TEGRA30_CLK_CLK_M_DIV4 },
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
4 */
5
6#include <linux/io.h>
7#include <linux/delay.h>
8#include <linux/clk-provider.h>

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578 { .con_id = "sclk", .dt_id = TEGRA30_CLK_SCLK },
579 { .con_id = "hclk", .dt_id = TEGRA30_CLK_HCLK },
580 { .con_id = "pclk", .dt_id = TEGRA30_CLK_PCLK },
581 { .con_id = "twd", .dt_id = TEGRA30_CLK_TWD },
582 { .con_id = "emc", .dt_id = TEGRA30_CLK_EMC },
583 { .con_id = "clk_32k", .dt_id = TEGRA30_CLK_CLK_32K },
584 { .con_id = "clk_m_div2", .dt_id = TEGRA30_CLK_CLK_M_DIV2 },
585 { .con_id = "clk_m_div4", .dt_id = TEGRA30_CLK_CLK_M_DIV4 },
586 { .con_id = "osc_div2", .dt_id = TEGRA30_CLK_OSC_DIV2 },
587 { .con_id = "osc_div4", .dt_id = TEGRA30_CLK_OSC_DIV4 },
586 { .con_id = "cml0", .dt_id = TEGRA30_CLK_CML0 },
587 { .con_id = "cml1", .dt_id = TEGRA30_CLK_CML1 },
588 { .con_id = "clk_m", .dt_id = TEGRA30_CLK_CLK_M },
589 { .con_id = "pll_ref", .dt_id = TEGRA30_CLK_PLL_REF },
590 { .con_id = "csus", .dev_id = "tengra_camera", .dt_id = TEGRA30_CLK_CSUS },
591 { .con_id = "vcp", .dev_id = "tegra-avp", .dt_id = TEGRA30_CLK_VCP },
592 { .con_id = "bsea", .dev_id = "tegra-avp", .dt_id = TEGRA30_CLK_BSEA },
593 { .con_id = "bsev", .dev_id = "tegra-aes", .dt_id = TEGRA30_CLK_BSEV },

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680 { .dev_id = "tegradc.1", .dt_id = TEGRA30_CLK_DSIB },
681};
682
683static struct tegra_clk tegra30_clks[tegra_clk_max] __initdata = {
684 [tegra_clk_clk_32k] = { .dt_id = TEGRA30_CLK_CLK_32K, .present = true },
685 [tegra_clk_clk_m] = { .dt_id = TEGRA30_CLK_CLK_M, .present = true },
686 [tegra_clk_clk_m_div2] = { .dt_id = TEGRA30_CLK_CLK_M_DIV2, .present = true },
687 [tegra_clk_clk_m_div4] = { .dt_id = TEGRA30_CLK_CLK_M_DIV4, .present = true },
588 { .con_id = "cml0", .dt_id = TEGRA30_CLK_CML0 },
589 { .con_id = "cml1", .dt_id = TEGRA30_CLK_CML1 },
590 { .con_id = "clk_m", .dt_id = TEGRA30_CLK_CLK_M },
591 { .con_id = "pll_ref", .dt_id = TEGRA30_CLK_PLL_REF },
592 { .con_id = "csus", .dev_id = "tengra_camera", .dt_id = TEGRA30_CLK_CSUS },
593 { .con_id = "vcp", .dev_id = "tegra-avp", .dt_id = TEGRA30_CLK_VCP },
594 { .con_id = "bsea", .dev_id = "tegra-avp", .dt_id = TEGRA30_CLK_BSEA },
595 { .con_id = "bsev", .dev_id = "tegra-aes", .dt_id = TEGRA30_CLK_BSEV },

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682 { .dev_id = "tegradc.1", .dt_id = TEGRA30_CLK_DSIB },
683};
684
685static struct tegra_clk tegra30_clks[tegra_clk_max] __initdata = {
686 [tegra_clk_clk_32k] = { .dt_id = TEGRA30_CLK_CLK_32K, .present = true },
687 [tegra_clk_clk_m] = { .dt_id = TEGRA30_CLK_CLK_M, .present = true },
688 [tegra_clk_clk_m_div2] = { .dt_id = TEGRA30_CLK_CLK_M_DIV2, .present = true },
689 [tegra_clk_clk_m_div4] = { .dt_id = TEGRA30_CLK_CLK_M_DIV4, .present = true },
690 [tegra_clk_osc_div2] = { .dt_id = TEGRA30_CLK_OSC_DIV2, .present = true },
691 [tegra_clk_osc_div4] = { .dt_id = TEGRA30_CLK_OSC_DIV4, .present = true },
688 [tegra_clk_pll_ref] = { .dt_id = TEGRA30_CLK_PLL_REF, .present = true },
689 [tegra_clk_spdif_in_sync] = { .dt_id = TEGRA30_CLK_SPDIF_IN_SYNC, .present = true },
690 [tegra_clk_i2s0_sync] = { .dt_id = TEGRA30_CLK_I2S0_SYNC, .present = true },
691 [tegra_clk_i2s1_sync] = { .dt_id = TEGRA30_CLK_I2S1_SYNC, .present = true },
692 [tegra_clk_i2s2_sync] = { .dt_id = TEGRA30_CLK_I2S2_SYNC, .present = true },
693 [tegra_clk_i2s3_sync] = { .dt_id = TEGRA30_CLK_I2S3_SYNC, .present = true },
694 [tegra_clk_i2s4_sync] = { .dt_id = TEGRA30_CLK_I2S4_SYNC, .present = true },
695 [tegra_clk_vimclk_sync] = { .dt_id = TEGRA30_CLK_VIMCLK_SYNC, .present = true },

--- 681 unchanged lines hidden --- 		692 [tegra_clk_pll_ref] = { .dt_id = TEGRA30_CLK_PLL_REF, .present = true },
693 [tegra_clk_spdif_in_sync] = { .dt_id = TEGRA30_CLK_SPDIF_IN_SYNC, .present = true },
694 [tegra_clk_i2s0_sync] = { .dt_id = TEGRA30_CLK_I2S0_SYNC, .present = true },
695 [tegra_clk_i2s1_sync] = { .dt_id = TEGRA30_CLK_I2S1_SYNC, .present = true },
696 [tegra_clk_i2s2_sync] = { .dt_id = TEGRA30_CLK_I2S2_SYNC, .present = true },
697 [tegra_clk_i2s3_sync] = { .dt_id = TEGRA30_CLK_I2S3_SYNC, .present = true },
698 [tegra_clk_i2s4_sync] = { .dt_id = TEGRA30_CLK_I2S4_SYNC, .present = true },
699 [tegra_clk_vimclk_sync] = { .dt_id = TEGRA30_CLK_VIMCLK_SYNC, .present = true },

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