clk-tegra210.c (bea1baa1e7722c82631fa263653c1279002dd273) clk-tegra210.c (88da44c5edb93d58f704fb9ea21962ca357d06a1)
1/*
2 * Copyright (c) 2012-2014 NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT

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2321 [tegra_clk_dmic2] = { .dt_id = TEGRA210_CLK_DMIC2, .present = true },
2322 [tegra_clk_dmic3] = { .dt_id = TEGRA210_CLK_DMIC3, .present = true },
2323 [tegra_clk_dmic1_sync_clk] = { .dt_id = TEGRA210_CLK_DMIC1_SYNC_CLK, .present = true },
2324 [tegra_clk_dmic2_sync_clk] = { .dt_id = TEGRA210_CLK_DMIC2_SYNC_CLK, .present = true },
2325 [tegra_clk_dmic3_sync_clk] = { .dt_id = TEGRA210_CLK_DMIC3_SYNC_CLK, .present = true },
2326 [tegra_clk_dmic1_sync_clk_mux] = { .dt_id = TEGRA210_CLK_DMIC1_SYNC_CLK_MUX, .present = true },
2327 [tegra_clk_dmic2_sync_clk_mux] = { .dt_id = TEGRA210_CLK_DMIC2_SYNC_CLK_MUX, .present = true },
2328 [tegra_clk_dmic3_sync_clk_mux] = { .dt_id = TEGRA210_CLK_DMIC3_SYNC_CLK_MUX, .present = true },
1/*
2 * Copyright (c) 2012-2014 NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT

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2321 [tegra_clk_dmic2] = { .dt_id = TEGRA210_CLK_DMIC2, .present = true },
2322 [tegra_clk_dmic3] = { .dt_id = TEGRA210_CLK_DMIC3, .present = true },
2323 [tegra_clk_dmic1_sync_clk] = { .dt_id = TEGRA210_CLK_DMIC1_SYNC_CLK, .present = true },
2324 [tegra_clk_dmic2_sync_clk] = { .dt_id = TEGRA210_CLK_DMIC2_SYNC_CLK, .present = true },
2325 [tegra_clk_dmic3_sync_clk] = { .dt_id = TEGRA210_CLK_DMIC3_SYNC_CLK, .present = true },
2326 [tegra_clk_dmic1_sync_clk_mux] = { .dt_id = TEGRA210_CLK_DMIC1_SYNC_CLK_MUX, .present = true },
2327 [tegra_clk_dmic2_sync_clk_mux] = { .dt_id = TEGRA210_CLK_DMIC2_SYNC_CLK_MUX, .present = true },
2328 [tegra_clk_dmic3_sync_clk_mux] = { .dt_id = TEGRA210_CLK_DMIC3_SYNC_CLK_MUX, .present = true },
2329 [tegra_clk_dp2] = { .dt_id = TEGRA210_CLK_DP2, .present = true },
2330 [tegra_clk_iqc1] = { .dt_id = TEGRA210_CLK_IQC1, .present = true },
2331 [tegra_clk_iqc2] = { .dt_id = TEGRA210_CLK_IQC2, .present = true },
2332 [tegra_clk_pll_a_out_adsp] = { .dt_id = TEGRA210_CLK_PLL_A_OUT_ADSP, .present = true },
2333 [tegra_clk_pll_a_out0_out_adsp] = { .dt_id = TEGRA210_CLK_PLL_A_OUT0_OUT_ADSP, .present = true },
2334 [tegra_clk_adsp] = { .dt_id = TEGRA210_CLK_ADSP, .present = true },
2335 [tegra_clk_adsp_neon] = { .dt_id = TEGRA210_CLK_ADSP_NEON, .present = true },
2329};
2330
2331static struct tegra_devclk devclks[] __initdata = {
2332 { .con_id = "clk_m", .dt_id = TEGRA210_CLK_CLK_M },
2333 { .con_id = "pll_ref", .dt_id = TEGRA210_CLK_PLL_REF },
2334 { .con_id = "clk_32k", .dt_id = TEGRA210_CLK_CLK_32K },
2335 { .con_id = "clk_m_div2", .dt_id = TEGRA210_CLK_CLK_M_DIV2 },
2336 { .con_id = "clk_m_div4", .dt_id = TEGRA210_CLK_CLK_M_DIV4 },

--- 830 unchanged lines hidden --- 		2336};
2337
2338static struct tegra_devclk devclks[] __initdata = {
2339 { .con_id = "clk_m", .dt_id = TEGRA210_CLK_CLK_M },
2340 { .con_id = "pll_ref", .dt_id = TEGRA210_CLK_PLL_REF },
2341 { .con_id = "clk_32k", .dt_id = TEGRA210_CLK_CLK_32K },
2342 { .con_id = "clk_m_div2", .dt_id = TEGRA210_CLK_CLK_M_DIV2 },
2343 { .con_id = "clk_m_div4", .dt_id = TEGRA210_CLK_CLK_M_DIV4 },

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