clk-tegra124.c (f26e8817b235d8764363bffcc9cbfc61867371f2) clk-tegra124.c (bfa34832df1fffb79c1719d4016e9cacf0f83b22)
1/*
2 * Copyright (c) 2012-2014 NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT

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923 [tegra_clk_audio1_mux] = { .dt_id = TEGRA124_CLK_AUDIO1_MUX, .present = true },
924 [tegra_clk_audio2_mux] = { .dt_id = TEGRA124_CLK_AUDIO2_MUX, .present = true },
925 [tegra_clk_audio3_mux] = { .dt_id = TEGRA124_CLK_AUDIO3_MUX, .present = true },
926 [tegra_clk_audio4_mux] = { .dt_id = TEGRA124_CLK_AUDIO4_MUX, .present = true },
927 [tegra_clk_spdif_mux] = { .dt_id = TEGRA124_CLK_SPDIF_MUX, .present = true },
928 [tegra_clk_clk_out_1_mux] = { .dt_id = TEGRA124_CLK_CLK_OUT_1_MUX, .present = true },
929 [tegra_clk_clk_out_2_mux] = { .dt_id = TEGRA124_CLK_CLK_OUT_2_MUX, .present = true },
930 [tegra_clk_clk_out_3_mux] = { .dt_id = TEGRA124_CLK_CLK_OUT_3_MUX, .present = true },
1/*
2 * Copyright (c) 2012-2014 NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT

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923 [tegra_clk_audio1_mux] = { .dt_id = TEGRA124_CLK_AUDIO1_MUX, .present = true },
924 [tegra_clk_audio2_mux] = { .dt_id = TEGRA124_CLK_AUDIO2_MUX, .present = true },
925 [tegra_clk_audio3_mux] = { .dt_id = TEGRA124_CLK_AUDIO3_MUX, .present = true },
926 [tegra_clk_audio4_mux] = { .dt_id = TEGRA124_CLK_AUDIO4_MUX, .present = true },
927 [tegra_clk_spdif_mux] = { .dt_id = TEGRA124_CLK_SPDIF_MUX, .present = true },
928 [tegra_clk_clk_out_1_mux] = { .dt_id = TEGRA124_CLK_CLK_OUT_1_MUX, .present = true },
929 [tegra_clk_clk_out_2_mux] = { .dt_id = TEGRA124_CLK_CLK_OUT_2_MUX, .present = true },
930 [tegra_clk_clk_out_3_mux] = { .dt_id = TEGRA124_CLK_CLK_OUT_3_MUX, .present = true },
931 [tegra_clk_cec] = { .dt_id = TEGRA124_CLK_CEC, .present = true },
931};
932
933static struct tegra_devclk devclks[] __initdata = {
934 { .con_id = "clk_m", .dt_id = TEGRA124_CLK_CLK_M },
935 { .con_id = "pll_ref", .dt_id = TEGRA124_CLK_PLL_REF },
936 { .con_id = "clk_32k", .dt_id = TEGRA124_CLK_CLK_32K },
937 { .con_id = "clk_m_div2", .dt_id = TEGRA124_CLK_CLK_M_DIV2 },
938 { .con_id = "clk_m_div4", .dt_id = TEGRA124_CLK_CLK_M_DIV4 },

--- 600 unchanged lines hidden --- 		932};
933
934static struct tegra_devclk devclks[] __initdata = {
935 { .con_id = "clk_m", .dt_id = TEGRA124_CLK_CLK_M },
936 { .con_id = "pll_ref", .dt_id = TEGRA124_CLK_PLL_REF },
937 { .con_id = "clk_32k", .dt_id = TEGRA124_CLK_CLK_32K },
938 { .con_id = "clk_m_div2", .dt_id = TEGRA124_CLK_CLK_M_DIV2 },
939 { .con_id = "clk_m_div4", .dt_id = TEGRA124_CLK_CLK_M_DIV4 },

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