clk-tegra124.c (e5f8a107d92db30a7ad7d8d95aee59f5ad76206a) clk-tegra124.c (da8d1a3555406275650b366460c6235f1696bf8b)
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (c) 2012-2014 NVIDIA CORPORATION. All rights reserved.
4 */
5
6#include <linux/io.h>
7#include <linux/clk-provider.h>
8#include <linux/clkdev.h>

--- 833 unchanged lines hidden (view full) ---

842 [tegra_clk_i2c6] = { .dt_id = TEGRA124_CLK_I2C6, .present = true },
843 [tegra_clk_vim2_clk] = { .dt_id = TEGRA124_CLK_VIM2_CLK, .present = true },
844 [tegra_clk_hdmi_audio] = { .dt_id = TEGRA124_CLK_HDMI_AUDIO, .present = true },
845 [tegra_clk_clk72Mhz] = { .dt_id = TEGRA124_CLK_CLK72MHZ, .present = true },
846 [tegra_clk_vic03] = { .dt_id = TEGRA124_CLK_VIC03, .present = true },
847 [tegra_clk_adx1] = { .dt_id = TEGRA124_CLK_ADX1, .present = true },
848 [tegra_clk_dpaux] = { .dt_id = TEGRA124_CLK_DPAUX, .present = true },
849 [tegra_clk_sor0] = { .dt_id = TEGRA124_CLK_SOR0, .present = true },
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (c) 2012-2014 NVIDIA CORPORATION. All rights reserved.
4 */
5
6#include <linux/io.h>
7#include <linux/clk-provider.h>
8#include <linux/clkdev.h>

--- 833 unchanged lines hidden (view full) ---

842 [tegra_clk_i2c6] = { .dt_id = TEGRA124_CLK_I2C6, .present = true },
843 [tegra_clk_vim2_clk] = { .dt_id = TEGRA124_CLK_VIM2_CLK, .present = true },
844 [tegra_clk_hdmi_audio] = { .dt_id = TEGRA124_CLK_HDMI_AUDIO, .present = true },
845 [tegra_clk_clk72Mhz] = { .dt_id = TEGRA124_CLK_CLK72MHZ, .present = true },
846 [tegra_clk_vic03] = { .dt_id = TEGRA124_CLK_VIC03, .present = true },
847 [tegra_clk_adx1] = { .dt_id = TEGRA124_CLK_ADX1, .present = true },
848 [tegra_clk_dpaux] = { .dt_id = TEGRA124_CLK_DPAUX, .present = true },
849 [tegra_clk_sor0] = { .dt_id = TEGRA124_CLK_SOR0, .present = true },
850 [tegra_clk_sor0_lvds] = { .dt_id = TEGRA124_CLK_SOR0_LVDS, .present = true },
850 [tegra_clk_sor0_out] = { .dt_id = TEGRA124_CLK_SOR0_OUT, .present = true },
851 [tegra_clk_gpu] = { .dt_id = TEGRA124_CLK_GPU, .present = true },
852 [tegra_clk_amx1] = { .dt_id = TEGRA124_CLK_AMX1, .present = true },
853 [tegra_clk_uartb] = { .dt_id = TEGRA124_CLK_UARTB, .present = true },
854 [tegra_clk_vfir] = { .dt_id = TEGRA124_CLK_VFIR, .present = true },
855 [tegra_clk_spdif_in] = { .dt_id = TEGRA124_CLK_SPDIF_IN, .present = true },
856 [tegra_clk_spdif_out] = { .dt_id = TEGRA124_CLK_SPDIF_OUT, .present = true },
857 [tegra_clk_vi_9] = { .dt_id = TEGRA124_CLK_VI, .present = true },
858 [tegra_clk_vi_sensor_8] = { .dt_id = TEGRA124_CLK_VI_SENSOR, .present = true },

--- 147 unchanged lines hidden (view full) ---

1006};
1007
1008static const char *mux_pllp_pllm_plld_plla_pllc_plld2_clkm[] = {
1009 "pll_p", "pll_m", "pll_d_out0", "pll_a_out0", "pll_c",
1010 "pll_d2_out0", "clk_m"
1011};
1012#define mux_pllp_pllm_plld_plla_pllc_plld2_clkm_idx NULL
1013
851 [tegra_clk_gpu] = { .dt_id = TEGRA124_CLK_GPU, .present = true },
852 [tegra_clk_amx1] = { .dt_id = TEGRA124_CLK_AMX1, .present = true },
853 [tegra_clk_uartb] = { .dt_id = TEGRA124_CLK_UARTB, .present = true },
854 [tegra_clk_vfir] = { .dt_id = TEGRA124_CLK_VFIR, .present = true },
855 [tegra_clk_spdif_in] = { .dt_id = TEGRA124_CLK_SPDIF_IN, .present = true },
856 [tegra_clk_spdif_out] = { .dt_id = TEGRA124_CLK_SPDIF_OUT, .present = true },
857 [tegra_clk_vi_9] = { .dt_id = TEGRA124_CLK_VI, .present = true },
858 [tegra_clk_vi_sensor_8] = { .dt_id = TEGRA124_CLK_VI_SENSOR, .present = true },

--- 147 unchanged lines hidden (view full) ---

1006};
1007
1008static const char *mux_pllp_pllm_plld_plla_pllc_plld2_clkm[] = {
1009 "pll_p", "pll_m", "pll_d_out0", "pll_a_out0", "pll_c",
1010 "pll_d2_out0", "clk_m"
1011};
1012#define mux_pllp_pllm_plld_plla_pllc_plld2_clkm_idx NULL
1013
1014static const char *mux_clkm_plldp_sor0lvds[] = {
1015 "clk_m", "pll_dp", "sor0_lvds",
1014static const char *mux_clkm_plldp_sor0out[] = {
1015 "clk_m", "pll_dp", "sor0_out",
1016};
1016};
1017#define mux_clkm_plldp_sor0lvds_idx NULL
1017#define mux_clkm_plldp_sor0out_idx NULL
1018
1019static struct tegra_periph_init_data tegra124_periph[] = {
1018
1019static struct tegra_periph_init_data tegra124_periph[] = {
1020 MUX8_NOGATE_LOCK("sor0_lvds", mux_pllp_pllm_plld_plla_pllc_plld2_clkm, CLK_SOURCE_SOR0, tegra_clk_sor0_lvds, &sor0_lock),
1021 NODIV("sor0", mux_clkm_plldp_sor0lvds, CLK_SOURCE_SOR0, 14, 3, 182, 0, tegra_clk_sor0, &sor0_lock),
1020 MUX8_NOGATE_LOCK("sor0_out", mux_pllp_pllm_plld_plla_pllc_plld2_clkm, CLK_SOURCE_SOR0, tegra_clk_sor0_out, &sor0_lock),
1021 NODIV("sor0", mux_clkm_plldp_sor0out, CLK_SOURCE_SOR0, 14, 3, 182, 0, tegra_clk_sor0, &sor0_lock),
1022};
1023
1024static struct clk **clks;
1025
1026static __init void tegra124_periph_clk_init(void __iomem *clk_base,
1027 void __iomem *pmc_base)
1028{
1029 struct clk *clk;

--- 554 unchanged lines hidden --- 		1022};
1023
1024static struct clk **clks;
1025
1026static __init void tegra124_periph_clk_init(void __iomem *clk_base,
1027 void __iomem *pmc_base)
1028{
1029 struct clk *clk;

--- 554 unchanged lines hidden ---