clk-tegra124.c (9a85eb4d62425555ccdc774d906e6bbca5ffccc0) clk-tegra124.c (2b50e49b093c6f4c03faaf06d6b67707fab40938)
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (c) 2012-2014 NVIDIA CORPORATION. All rights reserved.
4 */
5
6#include <linux/io.h>
7#include <linux/clk-provider.h>
8#include <linux/clkdev.h>

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857 [tegra_clk_vi_9] = { .dt_id = TEGRA124_CLK_VI, .present = true },
858 [tegra_clk_vi_sensor_8] = { .dt_id = TEGRA124_CLK_VI_SENSOR, .present = true },
859 [tegra_clk_fuse] = { .dt_id = TEGRA124_CLK_FUSE, .present = true },
860 [tegra_clk_fuse_burn] = { .dt_id = TEGRA124_CLK_FUSE_BURN, .present = true },
861 [tegra_clk_clk_32k] = { .dt_id = TEGRA124_CLK_CLK_32K, .present = true },
862 [tegra_clk_clk_m] = { .dt_id = TEGRA124_CLK_CLK_M, .present = true },
863 [tegra_clk_clk_m_div2] = { .dt_id = TEGRA124_CLK_CLK_M_DIV2, .present = true },
864 [tegra_clk_clk_m_div4] = { .dt_id = TEGRA124_CLK_CLK_M_DIV4, .present = true },
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (c) 2012-2014 NVIDIA CORPORATION. All rights reserved.
4 */
5
6#include <linux/io.h>
7#include <linux/clk-provider.h>
8#include <linux/clkdev.h>

--- 848 unchanged lines hidden (view full) ---

857 [tegra_clk_vi_9] = { .dt_id = TEGRA124_CLK_VI, .present = true },
858 [tegra_clk_vi_sensor_8] = { .dt_id = TEGRA124_CLK_VI_SENSOR, .present = true },
859 [tegra_clk_fuse] = { .dt_id = TEGRA124_CLK_FUSE, .present = true },
860 [tegra_clk_fuse_burn] = { .dt_id = TEGRA124_CLK_FUSE_BURN, .present = true },
861 [tegra_clk_clk_32k] = { .dt_id = TEGRA124_CLK_CLK_32K, .present = true },
862 [tegra_clk_clk_m] = { .dt_id = TEGRA124_CLK_CLK_M, .present = true },
863 [tegra_clk_clk_m_div2] = { .dt_id = TEGRA124_CLK_CLK_M_DIV2, .present = true },
864 [tegra_clk_clk_m_div4] = { .dt_id = TEGRA124_CLK_CLK_M_DIV4, .present = true },
865 [tegra_clk_osc] = { .dt_id = TEGRA124_CLK_OSC, .present = true },
865 [tegra_clk_osc_div2] = { .dt_id = TEGRA124_CLK_OSC_DIV2, .present = true },
866 [tegra_clk_osc_div4] = { .dt_id = TEGRA124_CLK_OSC_DIV4, .present = true },
867 [tegra_clk_pll_ref] = { .dt_id = TEGRA124_CLK_PLL_REF, .present = true },
868 [tegra_clk_pll_c] = { .dt_id = TEGRA124_CLK_PLL_C, .present = true },
869 [tegra_clk_pll_c_out1] = { .dt_id = TEGRA124_CLK_PLL_C_OUT1, .present = true },
870 [tegra_clk_pll_c2] = { .dt_id = TEGRA124_CLK_PLL_C2, .present = true },
871 [tegra_clk_pll_c3] = { .dt_id = TEGRA124_CLK_PLL_C3, .present = true },
872 [tegra_clk_pll_m] = { .dt_id = TEGRA124_CLK_PLL_M, .present = true },

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940};
941
942static struct tegra_devclk devclks[] __initdata = {
943 { .con_id = "clk_m", .dt_id = TEGRA124_CLK_CLK_M },
944 { .con_id = "pll_ref", .dt_id = TEGRA124_CLK_PLL_REF },
945 { .con_id = "clk_32k", .dt_id = TEGRA124_CLK_CLK_32K },
946 { .con_id = "clk_m_div2", .dt_id = TEGRA124_CLK_CLK_M_DIV2 },
947 { .con_id = "clk_m_div4", .dt_id = TEGRA124_CLK_CLK_M_DIV4 },
866 [tegra_clk_osc_div2] = { .dt_id = TEGRA124_CLK_OSC_DIV2, .present = true },
867 [tegra_clk_osc_div4] = { .dt_id = TEGRA124_CLK_OSC_DIV4, .present = true },
868 [tegra_clk_pll_ref] = { .dt_id = TEGRA124_CLK_PLL_REF, .present = true },
869 [tegra_clk_pll_c] = { .dt_id = TEGRA124_CLK_PLL_C, .present = true },
870 [tegra_clk_pll_c_out1] = { .dt_id = TEGRA124_CLK_PLL_C_OUT1, .present = true },
871 [tegra_clk_pll_c2] = { .dt_id = TEGRA124_CLK_PLL_C2, .present = true },
872 [tegra_clk_pll_c3] = { .dt_id = TEGRA124_CLK_PLL_C3, .present = true },
873 [tegra_clk_pll_m] = { .dt_id = TEGRA124_CLK_PLL_M, .present = true },

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941};
942
943static struct tegra_devclk devclks[] __initdata = {
944 { .con_id = "clk_m", .dt_id = TEGRA124_CLK_CLK_M },
945 { .con_id = "pll_ref", .dt_id = TEGRA124_CLK_PLL_REF },
946 { .con_id = "clk_32k", .dt_id = TEGRA124_CLK_CLK_32K },
947 { .con_id = "clk_m_div2", .dt_id = TEGRA124_CLK_CLK_M_DIV2 },
948 { .con_id = "clk_m_div4", .dt_id = TEGRA124_CLK_CLK_M_DIV4 },
949 { .con_id = "osc", .dt_id = TEGRA124_CLK_OSC },
948 { .con_id = "osc_div2", .dt_id = TEGRA124_CLK_OSC_DIV2 },
949 { .con_id = "osc_div4", .dt_id = TEGRA124_CLK_OSC_DIV4 },
950 { .con_id = "pll_c", .dt_id = TEGRA124_CLK_PLL_C },
951 { .con_id = "pll_c_out1", .dt_id = TEGRA124_CLK_PLL_C_OUT1 },
952 { .con_id = "pll_c2", .dt_id = TEGRA124_CLK_PLL_C2 },
953 { .con_id = "pll_c3", .dt_id = TEGRA124_CLK_PLL_C3 },
954 { .con_id = "pll_p", .dt_id = TEGRA124_CLK_PLL_P },
955 { .con_id = "pll_p_out1", .dt_id = TEGRA124_CLK_PLL_P_OUT1 },

--- 636 unchanged lines hidden --- 		950 { .con_id = "osc_div2", .dt_id = TEGRA124_CLK_OSC_DIV2 },
951 { .con_id = "osc_div4", .dt_id = TEGRA124_CLK_OSC_DIV4 },
952 { .con_id = "pll_c", .dt_id = TEGRA124_CLK_PLL_C },
953 { .con_id = "pll_c_out1", .dt_id = TEGRA124_CLK_PLL_C_OUT1 },
954 { .con_id = "pll_c2", .dt_id = TEGRA124_CLK_PLL_C2 },
955 { .con_id = "pll_c3", .dt_id = TEGRA124_CLK_PLL_C3 },
956 { .con_id = "pll_p", .dt_id = TEGRA124_CLK_PLL_P },
957 { .con_id = "pll_p_out1", .dt_id = TEGRA124_CLK_PLL_P_OUT1 },

--- 636 unchanged lines hidden ---