| clk-tegra124.c (82ba1c3c9988a8055f4a4d7ca2168e9efe7e7874) | clk-tegra124.c (20e7c323abac390deb35248705807bd844590048) |
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| 1/* 2 * Copyright (c) 2012, 2013, NVIDIA CORPORATION. All rights reserved. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms and conditions of the GNU General Public License, 6 * version 2, as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope it will be useful, but WITHOUT --- 747 unchanged lines hidden (view full) --- 756 .xtal_freq_count = 0xA4}, 757}; 758 759static struct tegra_clk tegra124_clks[tegra_clk_max] __initdata = { 760 [tegra_clk_ispb] = { .dt_id = TEGRA124_CLK_ISPB, .present = true }, 761 [tegra_clk_rtc] = { .dt_id = TEGRA124_CLK_RTC, .present = true }, 762 [tegra_clk_timer] = { .dt_id = TEGRA124_CLK_TIMER, .present = true }, 763 [tegra_clk_uarta] = { .dt_id = TEGRA124_CLK_UARTA, .present = true }, | 1/* 2 * Copyright (c) 2012, 2013, NVIDIA CORPORATION. All rights reserved. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms and conditions of the GNU General Public License, 6 * version 2, as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope it will be useful, but WITHOUT --- 747 unchanged lines hidden (view full) --- 756 .xtal_freq_count = 0xA4}, 757}; 758 759static struct tegra_clk tegra124_clks[tegra_clk_max] __initdata = { 760 [tegra_clk_ispb] = { .dt_id = TEGRA124_CLK_ISPB, .present = true }, 761 [tegra_clk_rtc] = { .dt_id = TEGRA124_CLK_RTC, .present = true }, 762 [tegra_clk_timer] = { .dt_id = TEGRA124_CLK_TIMER, .present = true }, 763 [tegra_clk_uarta] = { .dt_id = TEGRA124_CLK_UARTA, .present = true }, |
| 764 [tegra_clk_sdmmc2] = { .dt_id = TEGRA124_CLK_SDMMC2, .present = true }, | 764 [tegra_clk_sdmmc2_8] = { .dt_id = TEGRA124_CLK_SDMMC2, .present = true }, |
| 765 [tegra_clk_i2s1] = { .dt_id = TEGRA124_CLK_I2S1, .present = true }, 766 [tegra_clk_i2c1] = { .dt_id = TEGRA124_CLK_I2C1, .present = true }, 767 [tegra_clk_ndflash] = { .dt_id = TEGRA124_CLK_NDFLASH, .present = true }, | 765 [tegra_clk_i2s1] = { .dt_id = TEGRA124_CLK_I2S1, .present = true }, 766 [tegra_clk_i2c1] = { .dt_id = TEGRA124_CLK_I2C1, .present = true }, 767 [tegra_clk_ndflash] = { .dt_id = TEGRA124_CLK_NDFLASH, .present = true }, |
| 768 [tegra_clk_sdmmc1] = { .dt_id = TEGRA124_CLK_SDMMC1, .present = true }, 769 [tegra_clk_sdmmc4] = { .dt_id = TEGRA124_CLK_SDMMC4, .present = true }, | 768 [tegra_clk_sdmmc1_8] = { .dt_id = TEGRA124_CLK_SDMMC1, .present = true }, 769 [tegra_clk_sdmmc4_8] = { .dt_id = TEGRA124_CLK_SDMMC4, .present = true }, |
| 770 [tegra_clk_pwm] = { .dt_id = TEGRA124_CLK_PWM, .present = true }, 771 [tegra_clk_i2s2] = { .dt_id = TEGRA124_CLK_I2S2, .present = true }, 772 [tegra_clk_gr2d] = { .dt_id = TEGRA124_CLK_GR_2D, .present = true }, 773 [tegra_clk_usbd] = { .dt_id = TEGRA124_CLK_USBD, .present = true }, 774 [tegra_clk_isp_8] = { .dt_id = TEGRA124_CLK_ISP, .present = true }, 775 [tegra_clk_gr3d] = { .dt_id = TEGRA124_CLK_GR_3D, .present = true }, 776 [tegra_clk_disp2] = { .dt_id = TEGRA124_CLK_DISP2, .present = true }, 777 [tegra_clk_disp1] = { .dt_id = TEGRA124_CLK_DISP1, .present = true }, --- 19 unchanged lines hidden (view full) --- 797 [tegra_clk_usb2] = { .dt_id = TEGRA124_CLK_USB2, .present = true }, 798 [tegra_clk_usb3] = { .dt_id = TEGRA124_CLK_USB3, .present = true }, 799 [tegra_clk_vde_8] = { .dt_id = TEGRA124_CLK_VDE, .present = true }, 800 [tegra_clk_bsea] = { .dt_id = TEGRA124_CLK_BSEA, .present = true }, 801 [tegra_clk_bsev] = { .dt_id = TEGRA124_CLK_BSEV, .present = true }, 802 [tegra_clk_uartd] = { .dt_id = TEGRA124_CLK_UARTD, .present = true }, 803 [tegra_clk_i2c3] = { .dt_id = TEGRA124_CLK_I2C3, .present = true }, 804 [tegra_clk_sbc4] = { .dt_id = TEGRA124_CLK_SBC4, .present = true }, | 770 [tegra_clk_pwm] = { .dt_id = TEGRA124_CLK_PWM, .present = true }, 771 [tegra_clk_i2s2] = { .dt_id = TEGRA124_CLK_I2S2, .present = true }, 772 [tegra_clk_gr2d] = { .dt_id = TEGRA124_CLK_GR_2D, .present = true }, 773 [tegra_clk_usbd] = { .dt_id = TEGRA124_CLK_USBD, .present = true }, 774 [tegra_clk_isp_8] = { .dt_id = TEGRA124_CLK_ISP, .present = true }, 775 [tegra_clk_gr3d] = { .dt_id = TEGRA124_CLK_GR_3D, .present = true }, 776 [tegra_clk_disp2] = { .dt_id = TEGRA124_CLK_DISP2, .present = true }, 777 [tegra_clk_disp1] = { .dt_id = TEGRA124_CLK_DISP1, .present = true }, --- 19 unchanged lines hidden (view full) --- 797 [tegra_clk_usb2] = { .dt_id = TEGRA124_CLK_USB2, .present = true }, 798 [tegra_clk_usb3] = { .dt_id = TEGRA124_CLK_USB3, .present = true }, 799 [tegra_clk_vde_8] = { .dt_id = TEGRA124_CLK_VDE, .present = true }, 800 [tegra_clk_bsea] = { .dt_id = TEGRA124_CLK_BSEA, .present = true }, 801 [tegra_clk_bsev] = { .dt_id = TEGRA124_CLK_BSEV, .present = true }, 802 [tegra_clk_uartd] = { .dt_id = TEGRA124_CLK_UARTD, .present = true }, 803 [tegra_clk_i2c3] = { .dt_id = TEGRA124_CLK_I2C3, .present = true }, 804 [tegra_clk_sbc4] = { .dt_id = TEGRA124_CLK_SBC4, .present = true }, |
| 805 [tegra_clk_sdmmc3] = { .dt_id = TEGRA124_CLK_SDMMC3, .present = true }, | 805 [tegra_clk_sdmmc3_8] = { .dt_id = TEGRA124_CLK_SDMMC3, .present = true }, |
| 806 [tegra_clk_pcie] = { .dt_id = TEGRA124_CLK_PCIE, .present = true }, 807 [tegra_clk_owr] = { .dt_id = TEGRA124_CLK_OWR, .present = true }, 808 [tegra_clk_afi] = { .dt_id = TEGRA124_CLK_AFI, .present = true }, 809 [tegra_clk_csite] = { .dt_id = TEGRA124_CLK_CSITE, .present = true }, 810 [tegra_clk_la] = { .dt_id = TEGRA124_CLK_LA, .present = true }, 811 [tegra_clk_trace] = { .dt_id = TEGRA124_CLK_TRACE, .present = true }, 812 [tegra_clk_soc_therm] = { .dt_id = TEGRA124_CLK_SOC_THERM, .present = true }, 813 [tegra_clk_dtv] = { .dt_id = TEGRA124_CLK_DTV, .present = true }, --- 619 unchanged lines hidden --- | 806 [tegra_clk_pcie] = { .dt_id = TEGRA124_CLK_PCIE, .present = true }, 807 [tegra_clk_owr] = { .dt_id = TEGRA124_CLK_OWR, .present = true }, 808 [tegra_clk_afi] = { .dt_id = TEGRA124_CLK_AFI, .present = true }, 809 [tegra_clk_csite] = { .dt_id = TEGRA124_CLK_CSITE, .present = true }, 810 [tegra_clk_la] = { .dt_id = TEGRA124_CLK_LA, .present = true }, 811 [tegra_clk_trace] = { .dt_id = TEGRA124_CLK_TRACE, .present = true }, 812 [tegra_clk_soc_therm] = { .dt_id = TEGRA124_CLK_SOC_THERM, .present = true }, 813 [tegra_clk_dtv] = { .dt_id = TEGRA124_CLK_DTV, .present = true }, --- 619 unchanged lines hidden --- |