clk-tegra124.c (0c1d1210160f560841a48641d41b61ec7d05edb2) clk-tegra124.c (5c992afcf8e4f91fac05d39b86c7f7922a50145c)
1/*
2 * Copyright (c) 2012, 2013, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT

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25#include <linux/clk/tegra.h>
26#include <dt-bindings/clock/tegra124-car.h>
27
28#include "clk.h"
29#include "clk-id.h"
30
31#define CLK_SOURCE_CSITE 0x1d4
32#define CLK_SOURCE_EMC 0x19c
1/*
2 * Copyright (c) 2012, 2013, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT

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25#include <linux/clk/tegra.h>
26#include <dt-bindings/clock/tegra124-car.h>
27
28#include "clk.h"
29#include "clk-id.h"
30
31#define CLK_SOURCE_CSITE 0x1d4
32#define CLK_SOURCE_EMC 0x19c
33#define CLK_SOURCE_XUSB_SS_SRC 0x610
34
35#define PLLC_BASE 0x80
36#define PLLC_OUT 0x84
37#define PLLC_MISC2 0x88
38#define PLLC_MISC 0x8c
39#define PLLC2_BASE 0x4e8
40#define PLLC2_MISC 0x4ec
41#define PLLC3_BASE 0x4fc

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920 [tegra_clk_clk_out_1] = { .dt_id = TEGRA124_CLK_CLK_OUT_1, .present = true },
921 [tegra_clk_clk_out_2] = { .dt_id = TEGRA124_CLK_CLK_OUT_2, .present = true },
922 [tegra_clk_clk_out_3] = { .dt_id = TEGRA124_CLK_CLK_OUT_3, .present = true },
923 [tegra_clk_blink] = { .dt_id = TEGRA124_CLK_BLINK, .present = true },
924 [tegra_clk_xusb_host_src] = { .dt_id = TEGRA124_CLK_XUSB_HOST_SRC, .present = true },
925 [tegra_clk_xusb_falcon_src] = { .dt_id = TEGRA124_CLK_XUSB_FALCON_SRC, .present = true },
926 [tegra_clk_xusb_fs_src] = { .dt_id = TEGRA124_CLK_XUSB_FS_SRC, .present = true },
927 [tegra_clk_xusb_ss_src] = { .dt_id = TEGRA124_CLK_XUSB_SS_SRC, .present = true },
33
34#define PLLC_BASE 0x80
35#define PLLC_OUT 0x84
36#define PLLC_MISC2 0x88
37#define PLLC_MISC 0x8c
38#define PLLC2_BASE 0x4e8
39#define PLLC2_MISC 0x4ec
40#define PLLC3_BASE 0x4fc

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919 [tegra_clk_clk_out_1] = { .dt_id = TEGRA124_CLK_CLK_OUT_1, .present = true },
920 [tegra_clk_clk_out_2] = { .dt_id = TEGRA124_CLK_CLK_OUT_2, .present = true },
921 [tegra_clk_clk_out_3] = { .dt_id = TEGRA124_CLK_CLK_OUT_3, .present = true },
922 [tegra_clk_blink] = { .dt_id = TEGRA124_CLK_BLINK, .present = true },
923 [tegra_clk_xusb_host_src] = { .dt_id = TEGRA124_CLK_XUSB_HOST_SRC, .present = true },
924 [tegra_clk_xusb_falcon_src] = { .dt_id = TEGRA124_CLK_XUSB_FALCON_SRC, .present = true },
925 [tegra_clk_xusb_fs_src] = { .dt_id = TEGRA124_CLK_XUSB_FS_SRC, .present = true },
926 [tegra_clk_xusb_ss_src] = { .dt_id = TEGRA124_CLK_XUSB_SS_SRC, .present = true },
927 [tegra_clk_xusb_ss_div2] = { .dt_id = TEGRA124_CLK_XUSB_SS_DIV2, .present = true },
928 [tegra_clk_xusb_dev_src] = { .dt_id = TEGRA124_CLK_XUSB_DEV_SRC, .present = true },
929 [tegra_clk_xusb_dev] = { .dt_id = TEGRA124_CLK_XUSB_DEV, .present = true },
930 [tegra_clk_xusb_hs_src] = { .dt_id = TEGRA124_CLK_XUSB_HS_SRC, .present = true },
931 [tegra_clk_sclk] = { .dt_id = TEGRA124_CLK_SCLK, .present = true },
932 [tegra_clk_hclk] = { .dt_id = TEGRA124_CLK_HCLK, .present = true },
933 [tegra_clk_pclk] = { .dt_id = TEGRA124_CLK_PCLK, .present = true },
934 [tegra_clk_cclk_g] = { .dt_id = TEGRA124_CLK_CCLK_G, .present = true },
935 [tegra_clk_cclk_lp] = { .dt_id = TEGRA124_CLK_CCLK_LP, .present = true },

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1100 reg |= UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE;
1101 writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0);
1102}
1103
1104static __init void tegra124_periph_clk_init(void __iomem *clk_base,
1105 void __iomem *pmc_base)
1106{
1107 struct clk *clk;
928 [tegra_clk_xusb_dev_src] = { .dt_id = TEGRA124_CLK_XUSB_DEV_SRC, .present = true },
929 [tegra_clk_xusb_dev] = { .dt_id = TEGRA124_CLK_XUSB_DEV, .present = true },
930 [tegra_clk_xusb_hs_src] = { .dt_id = TEGRA124_CLK_XUSB_HS_SRC, .present = true },
931 [tegra_clk_sclk] = { .dt_id = TEGRA124_CLK_SCLK, .present = true },
932 [tegra_clk_hclk] = { .dt_id = TEGRA124_CLK_HCLK, .present = true },
933 [tegra_clk_pclk] = { .dt_id = TEGRA124_CLK_PCLK, .present = true },
934 [tegra_clk_cclk_g] = { .dt_id = TEGRA124_CLK_CCLK_G, .present = true },
935 [tegra_clk_cclk_lp] = { .dt_id = TEGRA124_CLK_CCLK_LP, .present = true },

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1100 reg |= UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE;
1101 writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0);
1102}
1103
1104static __init void tegra124_periph_clk_init(void __iomem *clk_base,
1105 void __iomem *pmc_base)
1106{
1107 struct clk *clk;
1108 u32 val;
1109
1108
1110 /* xusb_hs_src */
1111 val = readl(clk_base + CLK_SOURCE_XUSB_SS_SRC);
1112 val |= BIT(25); /* always select PLLU_60M */
1113 writel(val, clk_base + CLK_SOURCE_XUSB_SS_SRC);
1109 /* xusb_ss_div2 */
1110 clk = clk_register_fixed_factor(NULL, "xusb_ss_div2", "xusb_ss_src", 0,
1111 1, 2);
1112 clks[TEGRA124_CLK_XUSB_SS_DIV2] = clk;
1114
1113
1115 clk = clk_register_fixed_factor(NULL, "xusb_hs_src", "pll_u_60M", 0,
1116 1, 1);
1117 clks[TEGRA124_CLK_XUSB_HS_SRC] = clk;
1118
1119 /* dsia mux */
1120 clk = clk_register_mux(NULL, "dsia_mux", mux_plld_out0_plld2_out0,
1121 ARRAY_SIZE(mux_plld_out0_plld2_out0), 0,
1122 clk_base + PLLD_BASE, 25, 1, 0, &pll_d_lock);
1123 clks[TEGRA124_CLK_DSIA_MUX] = clk;
1124
1125 /* dsib mux */
1126 clk = clk_register_mux(NULL, "dsib_mux", mux_plld_out0_plld2_out0,

--- 301 unchanged lines hidden --- 		1114 /* dsia mux */
1115 clk = clk_register_mux(NULL, "dsia_mux", mux_plld_out0_plld2_out0,
1116 ARRAY_SIZE(mux_plld_out0_plld2_out0), 0,
1117 clk_base + PLLD_BASE, 25, 1, 0, &pll_d_lock);
1118 clks[TEGRA124_CLK_DSIA_MUX] = clk;
1119
1120 /* dsib mux */
1121 clk = clk_register_mux(NULL, "dsib_mux", mux_plld_out0_plld2_out0,

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