clk-tegra124.c (08acae34e8dadaa8c3a0a432760555bba1db8bfb) clk-tegra124.c (b270491eb9a033a1ab6c66e778c9dd3e3a4f7639)
1/*
2 * Copyright (c) 2012-2014 NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT

--- 122 unchanged lines hidden (view full) ---

131
132static void __iomem *clk_base;
133static void __iomem *pmc_base;
134
135static unsigned long osc_freq;
136static unsigned long pll_ref_freq;
137
138static DEFINE_SPINLOCK(pll_d_lock);
1/*
2 * Copyright (c) 2012-2014 NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT

--- 122 unchanged lines hidden (view full) ---

131
132static void __iomem *clk_base;
133static void __iomem *pmc_base;
134
135static unsigned long osc_freq;
136static unsigned long pll_ref_freq;
137
138static DEFINE_SPINLOCK(pll_d_lock);
139static DEFINE_SPINLOCK(pll_d2_lock);
140static DEFINE_SPINLOCK(pll_e_lock);
141static DEFINE_SPINLOCK(pll_re_lock);
142static DEFINE_SPINLOCK(pll_u_lock);
143static DEFINE_SPINLOCK(emc_lock);
144
145/* possible OSC frequencies in Hz */
146static unsigned long tegra124_input_freq[] = {
147 [0] = 13000000,
148 [1] = 16800000,
149 [4] = 19200000,
150 [5] = 38400000,
151 [8] = 12000000,
152 [9] = 48000000,
153 [12] = 260000000,
154};
155
139static DEFINE_SPINLOCK(pll_e_lock);
140static DEFINE_SPINLOCK(pll_re_lock);
141static DEFINE_SPINLOCK(pll_u_lock);
142static DEFINE_SPINLOCK(emc_lock);
143
144/* possible OSC frequencies in Hz */
145static unsigned long tegra124_input_freq[] = {
146 [0] = 13000000,
147 [1] = 16800000,
148 [4] = 19200000,
149 [5] = 38400000,
150 [8] = 12000000,
151 [9] = 48000000,
152 [12] = 260000000,
153};
154
156static const char *mux_plld_out0_plld2_out0[] = {
157 "pll_d_out0", "pll_d2_out0",
158};
159#define mux_plld_out0_plld2_out0_idx NULL
160
161static const char *mux_pllmcp_clkm[] = {
162 "pll_m", "pll_c", "pll_p", "clk_m", "pll_m_ud", "pll_c2", "pll_c3",
163};
164#define mux_pllmcp_clkm_idx NULL
165
166static struct div_nmp pllxc_nmp = {
167 .divm_shift = 0,
168 .divm_width = 8,

--- 617 unchanged lines hidden (view full) ---

786 [tegra_clk_apbdma] = { .dt_id = TEGRA124_CLK_APBDMA, .present = true },
787 [tegra_clk_kbc] = { .dt_id = TEGRA124_CLK_KBC, .present = true },
788 [tegra_clk_kfuse] = { .dt_id = TEGRA124_CLK_KFUSE, .present = true },
789 [tegra_clk_sbc1] = { .dt_id = TEGRA124_CLK_SBC1, .present = true },
790 [tegra_clk_nor] = { .dt_id = TEGRA124_CLK_NOR, .present = true },
791 [tegra_clk_sbc2] = { .dt_id = TEGRA124_CLK_SBC2, .present = true },
792 [tegra_clk_sbc3] = { .dt_id = TEGRA124_CLK_SBC3, .present = true },
793 [tegra_clk_i2c5] = { .dt_id = TEGRA124_CLK_I2C5, .present = true },
155static const char *mux_pllmcp_clkm[] = {
156 "pll_m", "pll_c", "pll_p", "clk_m", "pll_m_ud", "pll_c2", "pll_c3",
157};
158#define mux_pllmcp_clkm_idx NULL
159
160static struct div_nmp pllxc_nmp = {
161 .divm_shift = 0,
162 .divm_width = 8,

--- 617 unchanged lines hidden (view full) ---

780 [tegra_clk_apbdma] = { .dt_id = TEGRA124_CLK_APBDMA, .present = true },
781 [tegra_clk_kbc] = { .dt_id = TEGRA124_CLK_KBC, .present = true },
782 [tegra_clk_kfuse] = { .dt_id = TEGRA124_CLK_KFUSE, .present = true },
783 [tegra_clk_sbc1] = { .dt_id = TEGRA124_CLK_SBC1, .present = true },
784 [tegra_clk_nor] = { .dt_id = TEGRA124_CLK_NOR, .present = true },
785 [tegra_clk_sbc2] = { .dt_id = TEGRA124_CLK_SBC2, .present = true },
786 [tegra_clk_sbc3] = { .dt_id = TEGRA124_CLK_SBC3, .present = true },
787 [tegra_clk_i2c5] = { .dt_id = TEGRA124_CLK_I2C5, .present = true },
794 [tegra_clk_dsia] = { .dt_id = TEGRA124_CLK_DSIA, .present = true },
795 [tegra_clk_mipi] = { .dt_id = TEGRA124_CLK_MIPI, .present = true },
796 [tegra_clk_hdmi] = { .dt_id = TEGRA124_CLK_HDMI, .present = true },
797 [tegra_clk_csi] = { .dt_id = TEGRA124_CLK_CSI, .present = true },
798 [tegra_clk_i2c2] = { .dt_id = TEGRA124_CLK_I2C2, .present = true },
799 [tegra_clk_uartc] = { .dt_id = TEGRA124_CLK_UARTC, .present = true },
800 [tegra_clk_mipi_cal] = { .dt_id = TEGRA124_CLK_MIPI_CAL, .present = true },
801 [tegra_clk_emc] = { .dt_id = TEGRA124_CLK_EMC, .present = true },
802 [tegra_clk_usb2] = { .dt_id = TEGRA124_CLK_USB2, .present = true },

--- 9 unchanged lines hidden (view full) ---

812 [tegra_clk_owr] = { .dt_id = TEGRA124_CLK_OWR, .present = true },
813 [tegra_clk_afi] = { .dt_id = TEGRA124_CLK_AFI, .present = true },
814 [tegra_clk_csite] = { .dt_id = TEGRA124_CLK_CSITE, .present = true },
815 [tegra_clk_la] = { .dt_id = TEGRA124_CLK_LA, .present = true },
816 [tegra_clk_trace] = { .dt_id = TEGRA124_CLK_TRACE, .present = true },
817 [tegra_clk_soc_therm] = { .dt_id = TEGRA124_CLK_SOC_THERM, .present = true },
818 [tegra_clk_dtv] = { .dt_id = TEGRA124_CLK_DTV, .present = true },
819 [tegra_clk_i2cslow] = { .dt_id = TEGRA124_CLK_I2CSLOW, .present = true },
788 [tegra_clk_mipi] = { .dt_id = TEGRA124_CLK_MIPI, .present = true },
789 [tegra_clk_hdmi] = { .dt_id = TEGRA124_CLK_HDMI, .present = true },
790 [tegra_clk_csi] = { .dt_id = TEGRA124_CLK_CSI, .present = true },
791 [tegra_clk_i2c2] = { .dt_id = TEGRA124_CLK_I2C2, .present = true },
792 [tegra_clk_uartc] = { .dt_id = TEGRA124_CLK_UARTC, .present = true },
793 [tegra_clk_mipi_cal] = { .dt_id = TEGRA124_CLK_MIPI_CAL, .present = true },
794 [tegra_clk_emc] = { .dt_id = TEGRA124_CLK_EMC, .present = true },
795 [tegra_clk_usb2] = { .dt_id = TEGRA124_CLK_USB2, .present = true },

--- 9 unchanged lines hidden (view full) ---

805 [tegra_clk_owr] = { .dt_id = TEGRA124_CLK_OWR, .present = true },
806 [tegra_clk_afi] = { .dt_id = TEGRA124_CLK_AFI, .present = true },
807 [tegra_clk_csite] = { .dt_id = TEGRA124_CLK_CSITE, .present = true },
808 [tegra_clk_la] = { .dt_id = TEGRA124_CLK_LA, .present = true },
809 [tegra_clk_trace] = { .dt_id = TEGRA124_CLK_TRACE, .present = true },
810 [tegra_clk_soc_therm] = { .dt_id = TEGRA124_CLK_SOC_THERM, .present = true },
811 [tegra_clk_dtv] = { .dt_id = TEGRA124_CLK_DTV, .present = true },
812 [tegra_clk_i2cslow] = { .dt_id = TEGRA124_CLK_I2CSLOW, .present = true },
820 [tegra_clk_dsib] = { .dt_id = TEGRA124_CLK_DSIB, .present = true },
821 [tegra_clk_tsec] = { .dt_id = TEGRA124_CLK_TSEC, .present = true },
822 [tegra_clk_xusb_host] = { .dt_id = TEGRA124_CLK_XUSB_HOST, .present = true },
823 [tegra_clk_msenc] = { .dt_id = TEGRA124_CLK_MSENC, .present = true },
824 [tegra_clk_csus] = { .dt_id = TEGRA124_CLK_CSUS, .present = true },
825 [tegra_clk_mselect] = { .dt_id = TEGRA124_CLK_MSELECT, .present = true },
826 [tegra_clk_tsensor] = { .dt_id = TEGRA124_CLK_TSENSOR, .present = true },
827 [tegra_clk_i2s3] = { .dt_id = TEGRA124_CLK_I2S3, .present = true },
828 [tegra_clk_i2s4] = { .dt_id = TEGRA124_CLK_I2S4, .present = true },

--- 123 unchanged lines hidden (view full) ---

952 [tegra_clk_audio1_mux] = { .dt_id = TEGRA124_CLK_AUDIO1_MUX, .present = true },
953 [tegra_clk_audio2_mux] = { .dt_id = TEGRA124_CLK_AUDIO2_MUX, .present = true },
954 [tegra_clk_audio3_mux] = { .dt_id = TEGRA124_CLK_AUDIO3_MUX, .present = true },
955 [tegra_clk_audio4_mux] = { .dt_id = TEGRA124_CLK_AUDIO4_MUX, .present = true },
956 [tegra_clk_spdif_mux] = { .dt_id = TEGRA124_CLK_SPDIF_MUX, .present = true },
957 [tegra_clk_clk_out_1_mux] = { .dt_id = TEGRA124_CLK_CLK_OUT_1_MUX, .present = true },
958 [tegra_clk_clk_out_2_mux] = { .dt_id = TEGRA124_CLK_CLK_OUT_2_MUX, .present = true },
959 [tegra_clk_clk_out_3_mux] = { .dt_id = TEGRA124_CLK_CLK_OUT_3_MUX, .present = true },
813 [tegra_clk_tsec] = { .dt_id = TEGRA124_CLK_TSEC, .present = true },
814 [tegra_clk_xusb_host] = { .dt_id = TEGRA124_CLK_XUSB_HOST, .present = true },
815 [tegra_clk_msenc] = { .dt_id = TEGRA124_CLK_MSENC, .present = true },
816 [tegra_clk_csus] = { .dt_id = TEGRA124_CLK_CSUS, .present = true },
817 [tegra_clk_mselect] = { .dt_id = TEGRA124_CLK_MSELECT, .present = true },
818 [tegra_clk_tsensor] = { .dt_id = TEGRA124_CLK_TSENSOR, .present = true },
819 [tegra_clk_i2s3] = { .dt_id = TEGRA124_CLK_I2S3, .present = true },
820 [tegra_clk_i2s4] = { .dt_id = TEGRA124_CLK_I2S4, .present = true },

--- 123 unchanged lines hidden (view full) ---

944 [tegra_clk_audio1_mux] = { .dt_id = TEGRA124_CLK_AUDIO1_MUX, .present = true },
945 [tegra_clk_audio2_mux] = { .dt_id = TEGRA124_CLK_AUDIO2_MUX, .present = true },
946 [tegra_clk_audio3_mux] = { .dt_id = TEGRA124_CLK_AUDIO3_MUX, .present = true },
947 [tegra_clk_audio4_mux] = { .dt_id = TEGRA124_CLK_AUDIO4_MUX, .present = true },
948 [tegra_clk_spdif_mux] = { .dt_id = TEGRA124_CLK_SPDIF_MUX, .present = true },
949 [tegra_clk_clk_out_1_mux] = { .dt_id = TEGRA124_CLK_CLK_OUT_1_MUX, .present = true },
950 [tegra_clk_clk_out_2_mux] = { .dt_id = TEGRA124_CLK_CLK_OUT_2_MUX, .present = true },
951 [tegra_clk_clk_out_3_mux] = { .dt_id = TEGRA124_CLK_CLK_OUT_3_MUX, .present = true },
960 [tegra_clk_dsia_mux] = { .dt_id = TEGRA124_CLK_DSIA_MUX, .present = true },
961 [tegra_clk_dsib_mux] = { .dt_id = TEGRA124_CLK_DSIB_MUX, .present = true },
962};
963
964static struct tegra_devclk devclks[] __initdata = {
965 { .con_id = "clk_m", .dt_id = TEGRA124_CLK_CLK_M },
966 { .con_id = "pll_ref", .dt_id = TEGRA124_CLK_PLL_REF },
967 { .con_id = "clk_32k", .dt_id = TEGRA124_CLK_CLK_32K },
968 { .con_id = "clk_m_div2", .dt_id = TEGRA124_CLK_CLK_M_DIV2 },
969 { .con_id = "clk_m_div4", .dt_id = TEGRA124_CLK_CLK_M_DIV4 },

--- 145 unchanged lines hidden (view full) ---

1115{
1116 struct clk *clk;
1117
1118 /* xusb_ss_div2 */
1119 clk = clk_register_fixed_factor(NULL, "xusb_ss_div2", "xusb_ss_src", 0,
1120 1, 2);
1121 clks[TEGRA124_CLK_XUSB_SS_DIV2] = clk;
1122
952};
953
954static struct tegra_devclk devclks[] __initdata = {
955 { .con_id = "clk_m", .dt_id = TEGRA124_CLK_CLK_M },
956 { .con_id = "pll_ref", .dt_id = TEGRA124_CLK_PLL_REF },
957 { .con_id = "clk_32k", .dt_id = TEGRA124_CLK_CLK_32K },
958 { .con_id = "clk_m_div2", .dt_id = TEGRA124_CLK_CLK_M_DIV2 },
959 { .con_id = "clk_m_div4", .dt_id = TEGRA124_CLK_CLK_M_DIV4 },

--- 145 unchanged lines hidden (view full) ---

1105{
1106 struct clk *clk;
1107
1108 /* xusb_ss_div2 */
1109 clk = clk_register_fixed_factor(NULL, "xusb_ss_div2", "xusb_ss_src", 0,
1110 1, 2);
1111 clks[TEGRA124_CLK_XUSB_SS_DIV2] = clk;
1112
1123 /* dsia mux */
1124 clk = clk_register_mux(NULL, "dsia_mux", mux_plld_out0_plld2_out0,
1125 ARRAY_SIZE(mux_plld_out0_plld2_out0), 0,
1126 clk_base + PLLD_BASE, 25, 1, 0, &pll_d_lock);
1127 clks[TEGRA124_CLK_DSIA_MUX] = clk;
1113 clk = clk_register_gate(NULL, "plld_dsi", "plld_out0", 0,
1114 clk_base + PLLD_MISC, 30, 0, &pll_d_lock);
1115 clks[TEGRA124_CLK_PLLD_DSI] = clk;
1128
1116
1129 /* dsib mux */
1130 clk = clk_register_mux(NULL, "dsib_mux", mux_plld_out0_plld2_out0,
1131 ARRAY_SIZE(mux_plld_out0_plld2_out0), 0,
1132 clk_base + PLLD2_BASE, 25, 1, 0, &pll_d2_lock);
1133 clks[TEGRA124_CLK_DSIB_MUX] = clk;
1117 clk = tegra_clk_register_periph_gate("dsia", "plld_dsi", 0, clk_base,
1118 0, 48, periph_clk_enb_refcnt);
1119 clks[TEGRA124_CLK_DSIA] = clk;
1134
1120
1121 clk = tegra_clk_register_periph_gate("dsib", "plld_dsi", 0, clk_base,
1122 0, 82, periph_clk_enb_refcnt);
1123 clks[TEGRA124_CLK_DSIB] = clk;
1124
1135 /* emc mux */
1136 clk = clk_register_mux(NULL, "emc_mux", mux_pllmcp_clkm,
1137 ARRAY_SIZE(mux_pllmcp_clkm), 0,
1138 clk_base + CLK_SOURCE_EMC,
1139 29, 3, 0, &emc_lock);
1140
1141 clk = tegra_clk_register_mc("mc", "emc_mux", clk_base + CLK_SOURCE_EMC,
1142 &emc_lock);

--- 309 unchanged lines hidden (view full) ---

1452 * with a few clocks controlled by the PMC IP block. Everything in
1453 * this function should be common to Tegra124 and Tegra132. XXX The
1454 * PMC clock initialization should probably be moved to PMC-specific
1455 * driver code. No return value.
1456 */
1457static void __init tegra124_132_clock_init_pre(struct device_node *np)
1458{
1459 struct device_node *node;
1125 /* emc mux */
1126 clk = clk_register_mux(NULL, "emc_mux", mux_pllmcp_clkm,
1127 ARRAY_SIZE(mux_pllmcp_clkm), 0,
1128 clk_base + CLK_SOURCE_EMC,
1129 29, 3, 0, &emc_lock);
1130
1131 clk = tegra_clk_register_mc("mc", "emc_mux", clk_base + CLK_SOURCE_EMC,
1132 &emc_lock);

--- 309 unchanged lines hidden (view full) ---

1442 * with a few clocks controlled by the PMC IP block. Everything in
1443 * this function should be common to Tegra124 and Tegra132. XXX The
1444 * PMC clock initialization should probably be moved to PMC-specific
1445 * driver code. No return value.
1446 */
1447static void __init tegra124_132_clock_init_pre(struct device_node *np)
1448{
1449 struct device_node *node;
1450 u32 plld_base;
1460
1461 clk_base = of_iomap(np, 0);
1462 if (!clk_base) {
1463 pr_err("ioremap tegra124/tegra132 CAR failed\n");
1464 return;
1465 }
1466
1467 node = of_find_matching_node(NULL, pmc_match);

--- 19 unchanged lines hidden (view full) ---

1487 ARRAY_SIZE(tegra124_input_freq), &osc_freq, &pll_ref_freq) < 0)
1488 return;
1489
1490 tegra_fixed_clk_init(tegra124_clks);
1491 tegra124_pll_init(clk_base, pmc_base);
1492 tegra124_periph_clk_init(clk_base, pmc_base);
1493 tegra_audio_clk_init(clk_base, pmc_base, tegra124_clks, &pll_a_params);
1494 tegra_pmc_clk_init(pmc_base, tegra124_clks);
1451
1452 clk_base = of_iomap(np, 0);
1453 if (!clk_base) {
1454 pr_err("ioremap tegra124/tegra132 CAR failed\n");
1455 return;
1456 }
1457
1458 node = of_find_matching_node(NULL, pmc_match);

--- 19 unchanged lines hidden (view full) ---

1478 ARRAY_SIZE(tegra124_input_freq), &osc_freq, &pll_ref_freq) < 0)
1479 return;
1480
1481 tegra_fixed_clk_init(tegra124_clks);
1482 tegra124_pll_init(clk_base, pmc_base);
1483 tegra124_periph_clk_init(clk_base, pmc_base);
1484 tegra_audio_clk_init(clk_base, pmc_base, tegra124_clks, &pll_a_params);
1485 tegra_pmc_clk_init(pmc_base, tegra124_clks);
1486
1487 /* For Tegra124 & Tegra132, PLLD is the only source for DSIA & DSIB */
1488 plld_base = clk_readl(clk_base + PLLD_BASE);
1489 plld_base &= ~BIT(25);
1490 clk_writel(plld_base, clk_base + PLLD_BASE);
1495}
1496
1497/**
1498 * tegra124_132_clock_init_post - clock initialization postamble for T124/T132
1499 * @np: struct device_node * of the DT node for the SoC CAR IP block
1500 *
1501 * Register most of the along with a few clocks controlled by the PMC
1502 * IP block. Everything in this function should be common to Tegra124

--- 61 unchanged lines hidden --- 		1491}
1492
1493/**
1494 * tegra124_132_clock_init_post - clock initialization postamble for T124/T132
1495 * @np: struct device_node * of the DT node for the SoC CAR IP block
1496 *
1497 * Register most of the along with a few clocks controlled by the PMC
1498 * IP block. Everything in this function should be common to Tegra124

--- 61 unchanged lines hidden ---