clk-tegra114.c - OpenGrok cross reference for /linux/drivers/clk/tegra/clk-tegra114.c

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clk-tegra114.c (a3b072cd180c12e8fe0ece9487b9065808327640)	clk-tegra114.c (20e7c323abac390deb35248705807bd844590048)
1/* 2 * Copyright (c) 2012, 2013, NVIDIA CORPORATION. All rights reserved. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms and conditions of the GNU General Public License, 6 * version 2, as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope it will be useful, but WITHOUT --- 668 unchanged lines hidden (view full) --- 677 { .val = 0, .div = 0 }, 678}; 679 680static struct tegra_clk tegra114_clks[tegra_clk_max] __initdata = { 681 [tegra_clk_rtc] = { .dt_id = TEGRA114_CLK_RTC, .present = true }, 682 [tegra_clk_timer] = { .dt_id = TEGRA114_CLK_TIMER, .present = true }, 683 [tegra_clk_uarta] = { .dt_id = TEGRA114_CLK_UARTA, .present = true }, 684 [tegra_clk_uartd] = { .dt_id = TEGRA114_CLK_UARTD, .present = true },	1/* 2 * Copyright (c) 2012, 2013, NVIDIA CORPORATION. All rights reserved. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms and conditions of the GNU General Public License, 6 * version 2, as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope it will be useful, but WITHOUT --- 668 unchanged lines hidden (view full) --- 677 { .val = 0, .div = 0 }, 678}; 679 680static struct tegra_clk tegra114_clks[tegra_clk_max] __initdata = { 681 [tegra_clk_rtc] = { .dt_id = TEGRA114_CLK_RTC, .present = true }, 682 [tegra_clk_timer] = { .dt_id = TEGRA114_CLK_TIMER, .present = true }, 683 [tegra_clk_uarta] = { .dt_id = TEGRA114_CLK_UARTA, .present = true }, 684 [tegra_clk_uartd] = { .dt_id = TEGRA114_CLK_UARTD, .present = true },
685 [tegra_clk_sdmmc2] = { .dt_id = TEGRA114_CLK_SDMMC2, .present = true },	685 [tegra_clk_sdmmc2_8] = { .dt_id = TEGRA114_CLK_SDMMC2, .present = true },
686 [tegra_clk_i2s1] = { .dt_id = TEGRA114_CLK_I2S1, .present = true }, 687 [tegra_clk_i2c1] = { .dt_id = TEGRA114_CLK_I2C1, .present = true }, 688 [tegra_clk_ndflash] = { .dt_id = TEGRA114_CLK_NDFLASH, .present = true },	686 [tegra_clk_i2s1] = { .dt_id = TEGRA114_CLK_I2S1, .present = true }, 687 [tegra_clk_i2c1] = { .dt_id = TEGRA114_CLK_I2C1, .present = true }, 688 [tegra_clk_ndflash] = { .dt_id = TEGRA114_CLK_NDFLASH, .present = true },
689 [tegra_clk_sdmmc1] = { .dt_id = TEGRA114_CLK_SDMMC1, .present = true }, 690 [tegra_clk_sdmmc4] = { .dt_id = TEGRA114_CLK_SDMMC4, .present = true },	689 [tegra_clk_sdmmc1_8] = { .dt_id = TEGRA114_CLK_SDMMC1, .present = true }, 690 [tegra_clk_sdmmc4_8] = { .dt_id = TEGRA114_CLK_SDMMC4, .present = true },
691 [tegra_clk_pwm] = { .dt_id = TEGRA114_CLK_PWM, .present = true }, 692 [tegra_clk_i2s0] = { .dt_id = TEGRA114_CLK_I2S0, .present = true }, 693 [tegra_clk_i2s2] = { .dt_id = TEGRA114_CLK_I2S2, .present = true }, 694 [tegra_clk_epp_8] = { .dt_id = TEGRA114_CLK_EPP, .present = true }, 695 [tegra_clk_gr2d_8] = { .dt_id = TEGRA114_CLK_GR2D, .present = true }, 696 [tegra_clk_usbd] = { .dt_id = TEGRA114_CLK_USBD, .present = true }, 697 [tegra_clk_isp] = { .dt_id = TEGRA114_CLK_ISP, .present = true }, 698 [tegra_clk_gr3d_8] = { .dt_id = TEGRA114_CLK_GR3D, .present = true }, --- 19 unchanged lines hidden (view full) --- 718 [tegra_clk_emc] = { .dt_id = TEGRA114_CLK_EMC, .present = true }, 719 [tegra_clk_usb2] = { .dt_id = TEGRA114_CLK_USB2, .present = true }, 720 [tegra_clk_usb3] = { .dt_id = TEGRA114_CLK_USB3, .present = true }, 721 [tegra_clk_vde_8] = { .dt_id = TEGRA114_CLK_VDE, .present = true }, 722 [tegra_clk_bsea] = { .dt_id = TEGRA114_CLK_BSEA, .present = true }, 723 [tegra_clk_bsev] = { .dt_id = TEGRA114_CLK_BSEV, .present = true }, 724 [tegra_clk_i2c3] = { .dt_id = TEGRA114_CLK_I2C3, .present = true }, 725 [tegra_clk_sbc4_8] = { .dt_id = TEGRA114_CLK_SBC4, .present = true },	691 [tegra_clk_pwm] = { .dt_id = TEGRA114_CLK_PWM, .present = true }, 692 [tegra_clk_i2s0] = { .dt_id = TEGRA114_CLK_I2S0, .present = true }, 693 [tegra_clk_i2s2] = { .dt_id = TEGRA114_CLK_I2S2, .present = true }, 694 [tegra_clk_epp_8] = { .dt_id = TEGRA114_CLK_EPP, .present = true }, 695 [tegra_clk_gr2d_8] = { .dt_id = TEGRA114_CLK_GR2D, .present = true }, 696 [tegra_clk_usbd] = { .dt_id = TEGRA114_CLK_USBD, .present = true }, 697 [tegra_clk_isp] = { .dt_id = TEGRA114_CLK_ISP, .present = true }, 698 [tegra_clk_gr3d_8] = { .dt_id = TEGRA114_CLK_GR3D, .present = true }, --- 19 unchanged lines hidden (view full) --- 718 [tegra_clk_emc] = { .dt_id = TEGRA114_CLK_EMC, .present = true }, 719 [tegra_clk_usb2] = { .dt_id = TEGRA114_CLK_USB2, .present = true }, 720 [tegra_clk_usb3] = { .dt_id = TEGRA114_CLK_USB3, .present = true }, 721 [tegra_clk_vde_8] = { .dt_id = TEGRA114_CLK_VDE, .present = true }, 722 [tegra_clk_bsea] = { .dt_id = TEGRA114_CLK_BSEA, .present = true }, 723 [tegra_clk_bsev] = { .dt_id = TEGRA114_CLK_BSEV, .present = true }, 724 [tegra_clk_i2c3] = { .dt_id = TEGRA114_CLK_I2C3, .present = true }, 725 [tegra_clk_sbc4_8] = { .dt_id = TEGRA114_CLK_SBC4, .present = true },
726 [tegra_clk_sdmmc3] = { .dt_id = TEGRA114_CLK_SDMMC3, .present = true },	726 [tegra_clk_sdmmc3_8] = { .dt_id = TEGRA114_CLK_SDMMC3, .present = true },
727 [tegra_clk_owr] = { .dt_id = TEGRA114_CLK_OWR, .present = true }, 728 [tegra_clk_csite] = { .dt_id = TEGRA114_CLK_CSITE, .present = true }, 729 [tegra_clk_la] = { .dt_id = TEGRA114_CLK_LA, .present = true }, 730 [tegra_clk_trace] = { .dt_id = TEGRA114_CLK_TRACE, .present = true }, 731 [tegra_clk_soc_therm] = { .dt_id = TEGRA114_CLK_SOC_THERM, .present = true }, 732 [tegra_clk_dtv] = { .dt_id = TEGRA114_CLK_DTV, .present = true }, 733 [tegra_clk_ndspeed] = { .dt_id = TEGRA114_CLK_NDSPEED, .present = true }, 734 [tegra_clk_i2cslow] = { .dt_id = TEGRA114_CLK_I2CSLOW, .present = true }, --- 752 unchanged lines hidden ---	727 [tegra_clk_owr] = { .dt_id = TEGRA114_CLK_OWR, .present = true }, 728 [tegra_clk_csite] = { .dt_id = TEGRA114_CLK_CSITE, .present = true }, 729 [tegra_clk_la] = { .dt_id = TEGRA114_CLK_LA, .present = true }, 730 [tegra_clk_trace] = { .dt_id = TEGRA114_CLK_TRACE, .present = true }, 731 [tegra_clk_soc_therm] = { .dt_id = TEGRA114_CLK_SOC_THERM, .present = true }, 732 [tegra_clk_dtv] = { .dt_id = TEGRA114_CLK_DTV, .present = true }, 733 [tegra_clk_ndspeed] = { .dt_id = TEGRA114_CLK_NDSPEED, .present = true }, 734 [tegra_clk_i2cslow] = { .dt_id = TEGRA114_CLK_I2CSLOW, .present = true }, --- 752 unchanged lines hidden ---