clk-tegra114.c (879f99ef2c4c05d9a7f0a67a05f1415663119825) clk-tegra114.c (5c992afcf8e4f91fac05d39b86c7f7922a50145c)
1/*
2 * Copyright (c) 2012, 2013, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT

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137#define UTMIPLL_HW_PWRDN_CFG0_USE_LOCKDET BIT(6)
138#define UTMIPLL_HW_PWRDN_CFG0_SEQ_RESET_INPUT_VALUE BIT(5)
139#define UTMIPLL_HW_PWRDN_CFG0_SEQ_IN_SWCTL BIT(4)
140#define UTMIPLL_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL BIT(2)
141#define UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE BIT(1)
142#define UTMIPLL_HW_PWRDN_CFG0_IDDQ_SWCTL BIT(0)
143
144#define CLK_SOURCE_CSITE 0x1d4
1/*
2 * Copyright (c) 2012, 2013, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT

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137#define UTMIPLL_HW_PWRDN_CFG0_USE_LOCKDET BIT(6)
138#define UTMIPLL_HW_PWRDN_CFG0_SEQ_RESET_INPUT_VALUE BIT(5)
139#define UTMIPLL_HW_PWRDN_CFG0_SEQ_IN_SWCTL BIT(4)
140#define UTMIPLL_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL BIT(2)
141#define UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE BIT(1)
142#define UTMIPLL_HW_PWRDN_CFG0_IDDQ_SWCTL BIT(0)
143
144#define CLK_SOURCE_CSITE 0x1d4
145#define CLK_SOURCE_XUSB_SS_SRC 0x610
146#define CLK_SOURCE_EMC 0x19c
147
148/* PLLM override registers */
149#define PMC_PLLM_WB0_OVERRIDE 0x1dc
150#define PMC_PLLM_WB0_OVERRIDE_2 0x2b0
151
152/* Tegra CPU clock and reset control regs */
153#define CLK_RST_CONTROLLER_CPU_CMPLX_STATUS 0x470

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829 [tegra_clk_clk_out_1] = { .dt_id = TEGRA114_CLK_CLK_OUT_1, .present = true },
830 [tegra_clk_clk_out_2] = { .dt_id = TEGRA114_CLK_CLK_OUT_2, .present = true },
831 [tegra_clk_clk_out_3] = { .dt_id = TEGRA114_CLK_CLK_OUT_3, .present = true },
832 [tegra_clk_blink] = { .dt_id = TEGRA114_CLK_BLINK, .present = true },
833 [tegra_clk_xusb_host_src] = { .dt_id = TEGRA114_CLK_XUSB_HOST_SRC, .present = true },
834 [tegra_clk_xusb_falcon_src] = { .dt_id = TEGRA114_CLK_XUSB_FALCON_SRC, .present = true },
835 [tegra_clk_xusb_fs_src] = { .dt_id = TEGRA114_CLK_XUSB_FS_SRC, .present = true },
836 [tegra_clk_xusb_ss_src] = { .dt_id = TEGRA114_CLK_XUSB_SS_SRC, .present = true },
145#define CLK_SOURCE_EMC 0x19c
146
147/* PLLM override registers */
148#define PMC_PLLM_WB0_OVERRIDE 0x1dc
149#define PMC_PLLM_WB0_OVERRIDE_2 0x2b0
150
151/* Tegra CPU clock and reset control regs */
152#define CLK_RST_CONTROLLER_CPU_CMPLX_STATUS 0x470

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828 [tegra_clk_clk_out_1] = { .dt_id = TEGRA114_CLK_CLK_OUT_1, .present = true },
829 [tegra_clk_clk_out_2] = { .dt_id = TEGRA114_CLK_CLK_OUT_2, .present = true },
830 [tegra_clk_clk_out_3] = { .dt_id = TEGRA114_CLK_CLK_OUT_3, .present = true },
831 [tegra_clk_blink] = { .dt_id = TEGRA114_CLK_BLINK, .present = true },
832 [tegra_clk_xusb_host_src] = { .dt_id = TEGRA114_CLK_XUSB_HOST_SRC, .present = true },
833 [tegra_clk_xusb_falcon_src] = { .dt_id = TEGRA114_CLK_XUSB_FALCON_SRC, .present = true },
834 [tegra_clk_xusb_fs_src] = { .dt_id = TEGRA114_CLK_XUSB_FS_SRC, .present = true },
835 [tegra_clk_xusb_ss_src] = { .dt_id = TEGRA114_CLK_XUSB_SS_SRC, .present = true },
836 [tegra_clk_xusb_ss_div2] = { .dt_id = TEGRA114_CLK_XUSB_SS_DIV2, .present = true},
837 [tegra_clk_xusb_dev_src] = { .dt_id = TEGRA114_CLK_XUSB_DEV_SRC, .present = true },
838 [tegra_clk_xusb_dev] = { .dt_id = TEGRA114_CLK_XUSB_DEV, .present = true },
839 [tegra_clk_xusb_hs_src] = { .dt_id = TEGRA114_CLK_XUSB_HS_SRC, .present = true },
840 [tegra_clk_sclk] = { .dt_id = TEGRA114_CLK_SCLK, .present = true },
841 [tegra_clk_hclk] = { .dt_id = TEGRA114_CLK_HCLK, .present = true },
842 [tegra_clk_pclk] = { .dt_id = TEGRA114_CLK_PCLK, .present = true },
843 [tegra_clk_cclk_g] = { .dt_id = TEGRA114_CLK_CCLK_G, .present = true },
844 [tegra_clk_cclk_lp] = { .dt_id = TEGRA114_CLK_CCLK_LP, .present = true },

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1177 clk_base, 0, &pll_e_params, NULL);
1178 clks[TEGRA114_CLK_PLL_E_OUT0] = clk;
1179}
1180
1181static __init void tegra114_periph_clk_init(void __iomem *clk_base,
1182 void __iomem *pmc_base)
1183{
1184 struct clk *clk;
837 [tegra_clk_xusb_dev_src] = { .dt_id = TEGRA114_CLK_XUSB_DEV_SRC, .present = true },
838 [tegra_clk_xusb_dev] = { .dt_id = TEGRA114_CLK_XUSB_DEV, .present = true },
839 [tegra_clk_xusb_hs_src] = { .dt_id = TEGRA114_CLK_XUSB_HS_SRC, .present = true },
840 [tegra_clk_sclk] = { .dt_id = TEGRA114_CLK_SCLK, .present = true },
841 [tegra_clk_hclk] = { .dt_id = TEGRA114_CLK_HCLK, .present = true },
842 [tegra_clk_pclk] = { .dt_id = TEGRA114_CLK_PCLK, .present = true },
843 [tegra_clk_cclk_g] = { .dt_id = TEGRA114_CLK_CCLK_G, .present = true },
844 [tegra_clk_cclk_lp] = { .dt_id = TEGRA114_CLK_CCLK_LP, .present = true },

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1177 clk_base, 0, &pll_e_params, NULL);
1178 clks[TEGRA114_CLK_PLL_E_OUT0] = clk;
1179}
1180
1181static __init void tegra114_periph_clk_init(void __iomem *clk_base,
1182 void __iomem *pmc_base)
1183{
1184 struct clk *clk;
1185 u32 val;
1186
1185
1187 /* xusb_hs_src */
1188 val = readl(clk_base + CLK_SOURCE_XUSB_SS_SRC);
1189 val |= BIT(25); /* always select PLLU_60M */
1190 writel(val, clk_base + CLK_SOURCE_XUSB_SS_SRC);
1186 /* xusb_ss_div2 */
1187 clk = clk_register_fixed_factor(NULL, "xusb_ss_div2", "xusb_ss_src", 0,
1188 1, 2);
1189 clks[TEGRA114_CLK_XUSB_SS_DIV2] = clk;
1191
1190
1192 clk = clk_register_fixed_factor(NULL, "xusb_hs_src", "pll_u_60M", 0,
1193 1, 1);
1194 clks[TEGRA114_CLK_XUSB_HS_SRC] = clk;
1195
1196 /* dsia mux */
1197 clk = clk_register_mux(NULL, "dsia_mux", mux_plld_out0_plld2_out0,
1198 ARRAY_SIZE(mux_plld_out0_plld2_out0),
1199 CLK_SET_RATE_NO_REPARENT,
1200 clk_base + PLLD_BASE, 25, 1, 0, &pll_d_lock);
1201 clks[TEGRA114_CLK_DSIA_MUX] = clk;
1202
1203 /* dsib mux */

--- 283 unchanged lines hidden --- 		1191 /* dsia mux */
1192 clk = clk_register_mux(NULL, "dsia_mux", mux_plld_out0_plld2_out0,
1193 ARRAY_SIZE(mux_plld_out0_plld2_out0),
1194 CLK_SET_RATE_NO_REPARENT,
1195 clk_base + PLLD_BASE, 25, 1, 0, &pll_d_lock);
1196 clks[TEGRA114_CLK_DSIA_MUX] = clk;
1197
1198 /* dsib mux */

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