clk-tegra114.c (75bf465f0bc33e9b776a46d6a1b9b990f5fb7c37) clk-tegra114.c (9a85eb4d62425555ccdc774d906e6bbca5ffccc0)
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (c) 2012, 2013, NVIDIA CORPORATION. All rights reserved.
4 */
5
6#include <linux/io.h>
7#include <linux/clk-provider.h>
8#include <linux/of.h>

--- 723 unchanged lines hidden (view full) ---

732 [tegra_clk_spdif_out] = { .dt_id = TEGRA114_CLK_SPDIF_OUT, .present = true },
733 [tegra_clk_vi_8] = { .dt_id = TEGRA114_CLK_VI, .present = true },
734 [tegra_clk_fuse] = { .dt_id = TEGRA114_CLK_FUSE, .present = true },
735 [tegra_clk_fuse_burn] = { .dt_id = TEGRA114_CLK_FUSE_BURN, .present = true },
736 [tegra_clk_clk_32k] = { .dt_id = TEGRA114_CLK_CLK_32K, .present = true },
737 [tegra_clk_clk_m] = { .dt_id = TEGRA114_CLK_CLK_M, .present = true },
738 [tegra_clk_clk_m_div2] = { .dt_id = TEGRA114_CLK_CLK_M_DIV2, .present = true },
739 [tegra_clk_clk_m_div4] = { .dt_id = TEGRA114_CLK_CLK_M_DIV4, .present = true },
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (c) 2012, 2013, NVIDIA CORPORATION. All rights reserved.
4 */
5
6#include <linux/io.h>
7#include <linux/clk-provider.h>
8#include <linux/of.h>

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732 [tegra_clk_spdif_out] = { .dt_id = TEGRA114_CLK_SPDIF_OUT, .present = true },
733 [tegra_clk_vi_8] = { .dt_id = TEGRA114_CLK_VI, .present = true },
734 [tegra_clk_fuse] = { .dt_id = TEGRA114_CLK_FUSE, .present = true },
735 [tegra_clk_fuse_burn] = { .dt_id = TEGRA114_CLK_FUSE_BURN, .present = true },
736 [tegra_clk_clk_32k] = { .dt_id = TEGRA114_CLK_CLK_32K, .present = true },
737 [tegra_clk_clk_m] = { .dt_id = TEGRA114_CLK_CLK_M, .present = true },
738 [tegra_clk_clk_m_div2] = { .dt_id = TEGRA114_CLK_CLK_M_DIV2, .present = true },
739 [tegra_clk_clk_m_div4] = { .dt_id = TEGRA114_CLK_CLK_M_DIV4, .present = true },
740 [tegra_clk_osc_div2] = { .dt_id = TEGRA114_CLK_OSC_DIV2, .present = true },
741 [tegra_clk_osc_div4] = { .dt_id = TEGRA114_CLK_OSC_DIV4, .present = true },
740 [tegra_clk_pll_ref] = { .dt_id = TEGRA114_CLK_PLL_REF, .present = true },
741 [tegra_clk_pll_c] = { .dt_id = TEGRA114_CLK_PLL_C, .present = true },
742 [tegra_clk_pll_c_out1] = { .dt_id = TEGRA114_CLK_PLL_C_OUT1, .present = true },
743 [tegra_clk_pll_c2] = { .dt_id = TEGRA114_CLK_PLL_C2, .present = true },
744 [tegra_clk_pll_c3] = { .dt_id = TEGRA114_CLK_PLL_C3, .present = true },
745 [tegra_clk_pll_m] = { .dt_id = TEGRA114_CLK_PLL_M, .present = true },
746 [tegra_clk_pll_m_out1] = { .dt_id = TEGRA114_CLK_PLL_M_OUT1, .present = true },
747 [tegra_clk_pll_p] = { .dt_id = TEGRA114_CLK_PLL_P, .present = true },

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812};
813
814static struct tegra_devclk devclks[] __initdata = {
815 { .con_id = "clk_m", .dt_id = TEGRA114_CLK_CLK_M },
816 { .con_id = "pll_ref", .dt_id = TEGRA114_CLK_PLL_REF },
817 { .con_id = "clk_32k", .dt_id = TEGRA114_CLK_CLK_32K },
818 { .con_id = "clk_m_div2", .dt_id = TEGRA114_CLK_CLK_M_DIV2 },
819 { .con_id = "clk_m_div4", .dt_id = TEGRA114_CLK_CLK_M_DIV4 },
742 [tegra_clk_pll_ref] = { .dt_id = TEGRA114_CLK_PLL_REF, .present = true },
743 [tegra_clk_pll_c] = { .dt_id = TEGRA114_CLK_PLL_C, .present = true },
744 [tegra_clk_pll_c_out1] = { .dt_id = TEGRA114_CLK_PLL_C_OUT1, .present = true },
745 [tegra_clk_pll_c2] = { .dt_id = TEGRA114_CLK_PLL_C2, .present = true },
746 [tegra_clk_pll_c3] = { .dt_id = TEGRA114_CLK_PLL_C3, .present = true },
747 [tegra_clk_pll_m] = { .dt_id = TEGRA114_CLK_PLL_M, .present = true },
748 [tegra_clk_pll_m_out1] = { .dt_id = TEGRA114_CLK_PLL_M_OUT1, .present = true },
749 [tegra_clk_pll_p] = { .dt_id = TEGRA114_CLK_PLL_P, .present = true },

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814};
815
816static struct tegra_devclk devclks[] __initdata = {
817 { .con_id = "clk_m", .dt_id = TEGRA114_CLK_CLK_M },
818 { .con_id = "pll_ref", .dt_id = TEGRA114_CLK_PLL_REF },
819 { .con_id = "clk_32k", .dt_id = TEGRA114_CLK_CLK_32K },
820 { .con_id = "clk_m_div2", .dt_id = TEGRA114_CLK_CLK_M_DIV2 },
821 { .con_id = "clk_m_div4", .dt_id = TEGRA114_CLK_CLK_M_DIV4 },
822 { .con_id = "osc_div2", .dt_id = TEGRA114_CLK_OSC_DIV2 },
823 { .con_id = "osc_div4", .dt_id = TEGRA114_CLK_OSC_DIV4 },
820 { .con_id = "pll_c", .dt_id = TEGRA114_CLK_PLL_C },
821 { .con_id = "pll_c_out1", .dt_id = TEGRA114_CLK_PLL_C_OUT1 },
822 { .con_id = "pll_c2", .dt_id = TEGRA114_CLK_PLL_C2 },
823 { .con_id = "pll_c3", .dt_id = TEGRA114_CLK_PLL_C3 },
824 { .con_id = "pll_p", .dt_id = TEGRA114_CLK_PLL_P },
825 { .con_id = "pll_p_out1", .dt_id = TEGRA114_CLK_PLL_P_OUT1 },
826 { .con_id = "pll_p_out2", .dt_id = TEGRA114_CLK_PLL_P_OUT2 },
827 { .con_id = "pll_p_out3", .dt_id = TEGRA114_CLK_PLL_P_OUT3 },

--- 546 unchanged lines hidden --- 		824 { .con_id = "pll_c", .dt_id = TEGRA114_CLK_PLL_C },
825 { .con_id = "pll_c_out1", .dt_id = TEGRA114_CLK_PLL_C_OUT1 },
826 { .con_id = "pll_c2", .dt_id = TEGRA114_CLK_PLL_C2 },
827 { .con_id = "pll_c3", .dt_id = TEGRA114_CLK_PLL_C3 },
828 { .con_id = "pll_p", .dt_id = TEGRA114_CLK_PLL_P },
829 { .con_id = "pll_p_out1", .dt_id = TEGRA114_CLK_PLL_P_OUT1 },
830 { .con_id = "pll_p_out2", .dt_id = TEGRA114_CLK_PLL_P_OUT2 },
831 { .con_id = "pll_p_out3", .dt_id = TEGRA114_CLK_PLL_P_OUT3 },

--- 546 unchanged lines hidden ---