clk-tegra114.c (0c49cd295d42d0032af11d55e2140dbec11dc8d0) clk-tegra114.c (b270491eb9a033a1ab6c66e778c9dd3e3a4f7639)
1/*
2 * Copyright (c) 2012, 2013, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT

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710 [tegra_clk_apbdma] = { .dt_id = TEGRA114_CLK_APBDMA, .present = true },
711 [tegra_clk_kbc] = { .dt_id = TEGRA114_CLK_KBC, .present = true },
712 [tegra_clk_kfuse] = { .dt_id = TEGRA114_CLK_KFUSE, .present = true },
713 [tegra_clk_sbc1_8] = { .dt_id = TEGRA114_CLK_SBC1, .present = true },
714 [tegra_clk_nor] = { .dt_id = TEGRA114_CLK_NOR, .present = true },
715 [tegra_clk_sbc2_8] = { .dt_id = TEGRA114_CLK_SBC2, .present = true },
716 [tegra_clk_sbc3_8] = { .dt_id = TEGRA114_CLK_SBC3, .present = true },
717 [tegra_clk_i2c5] = { .dt_id = TEGRA114_CLK_I2C5, .present = true },
1/*
2 * Copyright (c) 2012, 2013, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT

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710 [tegra_clk_apbdma] = { .dt_id = TEGRA114_CLK_APBDMA, .present = true },
711 [tegra_clk_kbc] = { .dt_id = TEGRA114_CLK_KBC, .present = true },
712 [tegra_clk_kfuse] = { .dt_id = TEGRA114_CLK_KFUSE, .present = true },
713 [tegra_clk_sbc1_8] = { .dt_id = TEGRA114_CLK_SBC1, .present = true },
714 [tegra_clk_nor] = { .dt_id = TEGRA114_CLK_NOR, .present = true },
715 [tegra_clk_sbc2_8] = { .dt_id = TEGRA114_CLK_SBC2, .present = true },
716 [tegra_clk_sbc3_8] = { .dt_id = TEGRA114_CLK_SBC3, .present = true },
717 [tegra_clk_i2c5] = { .dt_id = TEGRA114_CLK_I2C5, .present = true },
718 [tegra_clk_dsia] = { .dt_id = TEGRA114_CLK_DSIA, .present = true },
719 [tegra_clk_mipi] = { .dt_id = TEGRA114_CLK_MIPI, .present = true },
720 [tegra_clk_hdmi] = { .dt_id = TEGRA114_CLK_HDMI, .present = true },
721 [tegra_clk_csi] = { .dt_id = TEGRA114_CLK_CSI, .present = true },
722 [tegra_clk_i2c2] = { .dt_id = TEGRA114_CLK_I2C2, .present = true },
723 [tegra_clk_uartc] = { .dt_id = TEGRA114_CLK_UARTC, .present = true },
724 [tegra_clk_mipi_cal] = { .dt_id = TEGRA114_CLK_MIPI_CAL, .present = true },
725 [tegra_clk_emc] = { .dt_id = TEGRA114_CLK_EMC, .present = true },
726 [tegra_clk_usb2] = { .dt_id = TEGRA114_CLK_USB2, .present = true },

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734 [tegra_clk_owr] = { .dt_id = TEGRA114_CLK_OWR, .present = true },
735 [tegra_clk_csite] = { .dt_id = TEGRA114_CLK_CSITE, .present = true },
736 [tegra_clk_la] = { .dt_id = TEGRA114_CLK_LA, .present = true },
737 [tegra_clk_trace] = { .dt_id = TEGRA114_CLK_TRACE, .present = true },
738 [tegra_clk_soc_therm] = { .dt_id = TEGRA114_CLK_SOC_THERM, .present = true },
739 [tegra_clk_dtv] = { .dt_id = TEGRA114_CLK_DTV, .present = true },
740 [tegra_clk_ndspeed] = { .dt_id = TEGRA114_CLK_NDSPEED, .present = true },
741 [tegra_clk_i2cslow] = { .dt_id = TEGRA114_CLK_I2CSLOW, .present = true },
718 [tegra_clk_mipi] = { .dt_id = TEGRA114_CLK_MIPI, .present = true },
719 [tegra_clk_hdmi] = { .dt_id = TEGRA114_CLK_HDMI, .present = true },
720 [tegra_clk_csi] = { .dt_id = TEGRA114_CLK_CSI, .present = true },
721 [tegra_clk_i2c2] = { .dt_id = TEGRA114_CLK_I2C2, .present = true },
722 [tegra_clk_uartc] = { .dt_id = TEGRA114_CLK_UARTC, .present = true },
723 [tegra_clk_mipi_cal] = { .dt_id = TEGRA114_CLK_MIPI_CAL, .present = true },
724 [tegra_clk_emc] = { .dt_id = TEGRA114_CLK_EMC, .present = true },
725 [tegra_clk_usb2] = { .dt_id = TEGRA114_CLK_USB2, .present = true },

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733 [tegra_clk_owr] = { .dt_id = TEGRA114_CLK_OWR, .present = true },
734 [tegra_clk_csite] = { .dt_id = TEGRA114_CLK_CSITE, .present = true },
735 [tegra_clk_la] = { .dt_id = TEGRA114_CLK_LA, .present = true },
736 [tegra_clk_trace] = { .dt_id = TEGRA114_CLK_TRACE, .present = true },
737 [tegra_clk_soc_therm] = { .dt_id = TEGRA114_CLK_SOC_THERM, .present = true },
738 [tegra_clk_dtv] = { .dt_id = TEGRA114_CLK_DTV, .present = true },
739 [tegra_clk_ndspeed] = { .dt_id = TEGRA114_CLK_NDSPEED, .present = true },
740 [tegra_clk_i2cslow] = { .dt_id = TEGRA114_CLK_I2CSLOW, .present = true },
742 [tegra_clk_dsib] = { .dt_id = TEGRA114_CLK_DSIB, .present = true },
743 [tegra_clk_tsec] = { .dt_id = TEGRA114_CLK_TSEC, .present = true },
744 [tegra_clk_xusb_host] = { .dt_id = TEGRA114_CLK_XUSB_HOST, .present = true },
745 [tegra_clk_msenc] = { .dt_id = TEGRA114_CLK_MSENC, .present = true },
746 [tegra_clk_csus] = { .dt_id = TEGRA114_CLK_CSUS, .present = true },
747 [tegra_clk_mselect] = { .dt_id = TEGRA114_CLK_MSELECT, .present = true },
748 [tegra_clk_tsensor] = { .dt_id = TEGRA114_CLK_TSENSOR, .present = true },
749 [tegra_clk_i2s3] = { .dt_id = TEGRA114_CLK_I2S3, .present = true },
750 [tegra_clk_i2s4] = { .dt_id = TEGRA114_CLK_I2S4, .present = true },

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1219
1220 /* dsib mux */
1221 clk = clk_register_mux(NULL, "dsib_mux", mux_plld_out0_plld2_out0,
1222 ARRAY_SIZE(mux_plld_out0_plld2_out0),
1223 CLK_SET_RATE_NO_REPARENT,
1224 clk_base + PLLD2_BASE, 25, 1, 0, &pll_d2_lock);
1225 clks[TEGRA114_CLK_DSIB_MUX] = clk;
1226
741 [tegra_clk_tsec] = { .dt_id = TEGRA114_CLK_TSEC, .present = true },
742 [tegra_clk_xusb_host] = { .dt_id = TEGRA114_CLK_XUSB_HOST, .present = true },
743 [tegra_clk_msenc] = { .dt_id = TEGRA114_CLK_MSENC, .present = true },
744 [tegra_clk_csus] = { .dt_id = TEGRA114_CLK_CSUS, .present = true },
745 [tegra_clk_mselect] = { .dt_id = TEGRA114_CLK_MSELECT, .present = true },
746 [tegra_clk_tsensor] = { .dt_id = TEGRA114_CLK_TSENSOR, .present = true },
747 [tegra_clk_i2s3] = { .dt_id = TEGRA114_CLK_I2S3, .present = true },
748 [tegra_clk_i2s4] = { .dt_id = TEGRA114_CLK_I2S4, .present = true },

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1217
1218 /* dsib mux */
1219 clk = clk_register_mux(NULL, "dsib_mux", mux_plld_out0_plld2_out0,
1220 ARRAY_SIZE(mux_plld_out0_plld2_out0),
1221 CLK_SET_RATE_NO_REPARENT,
1222 clk_base + PLLD2_BASE, 25, 1, 0, &pll_d2_lock);
1223 clks[TEGRA114_CLK_DSIB_MUX] = clk;
1224
1225 clk = tegra_clk_register_periph_gate("dsia", "dsia_mux", 0, clk_base,
1226 0, 48, periph_clk_enb_refcnt);
1227 clks[TEGRA114_CLK_DSIA] = clk;
1228
1229 clk = tegra_clk_register_periph_gate("dsib", "dsib_mux", 0, clk_base,
1230 0, 82, periph_clk_enb_refcnt);
1231 clks[TEGRA114_CLK_DSIB] = clk;
1232
1227 /* emc mux */
1228 clk = clk_register_mux(NULL, "emc_mux", mux_pllmcp_clkm,
1229 ARRAY_SIZE(mux_pllmcp_clkm),
1230 CLK_SET_RATE_NO_REPARENT,
1231 clk_base + CLK_SOURCE_EMC,
1232 29, 3, 0, &emc_lock);
1233
1234 clk = tegra_clk_register_mc("mc", "emc_mux", clk_base + CLK_SOURCE_EMC,

--- 286 unchanged lines hidden --- 		1233 /* emc mux */
1234 clk = clk_register_mux(NULL, "emc_mux", mux_pllmcp_clkm,
1235 ARRAY_SIZE(mux_pllmcp_clkm),
1236 CLK_SET_RATE_NO_REPARENT,
1237 clk_base + CLK_SOURCE_EMC,
1238 29, 3, 0, &emc_lock);
1239
1240 clk = tegra_clk_register_mc("mc", "emc_mux", clk_base + CLK_SOURCE_EMC,

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