| clk-dfll.h (8eaaae9937649f54beac7da582fa6cc6c79ae936) | clk-dfll.h (27ed2f7e7ca5c38a8ce695e58e6cf270c26f370b) |
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| 1/* 2 * clk-dfll.h - prototypes and macros for the Tegra DFLL clocksource driver 3 * Copyright (C) 2013 NVIDIA Corporation. All rights reserved. 4 * 5 * Aleksandr Frid <afrid@nvidia.com> 6 * Paul Walmsley <pwalmsley@nvidia.com> 7 * 8 * This program is free software; you can redistribute it and/or modify --- 11 unchanged lines hidden (view full) --- 20 21#include <linux/platform_device.h> 22#include <linux/reset.h> 23#include <linux/types.h> 24 25/** 26 * struct tegra_dfll_soc_data - SoC-specific hooks/integration for the DFLL driver 27 * @dev: struct device * that holds the OPP table for the DFLL | 1/* 2 * clk-dfll.h - prototypes and macros for the Tegra DFLL clocksource driver 3 * Copyright (C) 2013 NVIDIA Corporation. All rights reserved. 4 * 5 * Aleksandr Frid <afrid@nvidia.com> 6 * Paul Walmsley <pwalmsley@nvidia.com> 7 * 8 * This program is free software; you can redistribute it and/or modify --- 11 unchanged lines hidden (view full) --- 20 21#include <linux/platform_device.h> 22#include <linux/reset.h> 23#include <linux/types.h> 24 25/** 26 * struct tegra_dfll_soc_data - SoC-specific hooks/integration for the DFLL driver 27 * @dev: struct device * that holds the OPP table for the DFLL |
| 28 * @min_millivolts: minimum voltage (in mV) that the DFLL can operate 29 * @tune0_low: DFLL tuning register 0 (low voltage range) 30 * @tune0_high: DFLL tuning register 0 (high voltage range) 31 * @tune1: DFLL tuning register 1 | 28 * @cvb: CPU frequency table for this SoC |
| 32 * @init_clock_trimmers: callback to initialize clock trimmers 33 * @set_clock_trimmers_high: callback to tune clock trimmers for high voltage 34 * @set_clock_trimmers_low: callback to tune clock trimmers for low voltage 35 */ 36struct tegra_dfll_soc_data { 37 struct device *dev; | 29 * @init_clock_trimmers: callback to initialize clock trimmers 30 * @set_clock_trimmers_high: callback to tune clock trimmers for high voltage 31 * @set_clock_trimmers_low: callback to tune clock trimmers for low voltage 32 */ 33struct tegra_dfll_soc_data { 34 struct device *dev; |
| 38 unsigned int min_millivolts; 39 u32 tune0_low; 40 u32 tune0_high; 41 u32 tune1; | 35 const struct cvb_table *cvb; |
| 42 43 void (*init_clock_trimmers)(void); 44 void (*set_clock_trimmers_high)(void); 45 void (*set_clock_trimmers_low)(void); 46}; 47 48int tegra_dfll_register(struct platform_device *pdev, 49 struct tegra_dfll_soc_data *soc); 50int tegra_dfll_unregister(struct platform_device *pdev); 51int tegra_dfll_runtime_suspend(struct device *dev); 52int tegra_dfll_runtime_resume(struct device *dev); 53 54#endif /* __DRIVERS_CLK_TEGRA_CLK_DFLL_H */ | 36 37 void (*init_clock_trimmers)(void); 38 void (*set_clock_trimmers_high)(void); 39 void (*set_clock_trimmers_low)(void); 40}; 41 42int tegra_dfll_register(struct platform_device *pdev, 43 struct tegra_dfll_soc_data *soc); 44int tegra_dfll_unregister(struct platform_device *pdev); 45int tegra_dfll_runtime_suspend(struct device *dev); 46int tegra_dfll_runtime_resume(struct device *dev); 47 48#endif /* __DRIVERS_CLK_TEGRA_CLK_DFLL_H */ |