clk-dfll.c (1cbc99dfe5d7d686fd022647f4e489b5eb8e9068) clk-dfll.c (27ed2f7e7ca5c38a8ce695e58e6cf270c26f370b)
1/*
2 * clk-dfll.c - Tegra DFLL clock source common code
3 *
4 * Copyright (C) 2012-2014 NVIDIA Corporation. All rights reserved.
5 *
6 * Aleksandr Frid <afrid@nvidia.com>
7 * Paul Walmsley <pwalmsley@nvidia.com>
8 *

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50#include <linux/pm_opp.h>
51#include <linux/pm_runtime.h>
52#include <linux/regmap.h>
53#include <linux/regulator/consumer.h>
54#include <linux/reset.h>
55#include <linux/seq_file.h>
56
57#include "clk-dfll.h"
1/*
2 * clk-dfll.c - Tegra DFLL clock source common code
3 *
4 * Copyright (C) 2012-2014 NVIDIA Corporation. All rights reserved.
5 *
6 * Aleksandr Frid <afrid@nvidia.com>
7 * Paul Walmsley <pwalmsley@nvidia.com>
8 *

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50#include <linux/pm_opp.h>
51#include <linux/pm_runtime.h>
52#include <linux/regmap.h>
53#include <linux/regulator/consumer.h>
54#include <linux/reset.h>
55#include <linux/seq_file.h>
56
57#include "clk-dfll.h"
58#include "cvb.h"
58
59/*
60 * DFLL control registers - access via dfll_{readl,writel}
61 */
62
63/* DFLL_CTRL: DFLL control register */
64#define DFLL_CTRL 0x00
65#define DFLL_CTRL_MODE_MASK 0x03

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437 * Tune the DFLL oscillator parameters and the CPU clock shaper for
438 * the low-voltage range. These settings are valid for any voltage,
439 * but may not be optimal.
440 */
441static void dfll_tune_low(struct tegra_dfll *td)
442{
443 td->tune_range = DFLL_TUNE_LOW;
444
59
60/*
61 * DFLL control registers - access via dfll_{readl,writel}
62 */
63
64/* DFLL_CTRL: DFLL control register */
65#define DFLL_CTRL 0x00
66#define DFLL_CTRL_MODE_MASK 0x03

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438 * Tune the DFLL oscillator parameters and the CPU clock shaper for
439 * the low-voltage range. These settings are valid for any voltage,
440 * but may not be optimal.
441 */
442static void dfll_tune_low(struct tegra_dfll *td)
443{
444 td->tune_range = DFLL_TUNE_LOW;
445
445 dfll_writel(td, td->soc->tune0_low, DFLL_TUNE0);
446 dfll_writel(td, td->soc->tune1, DFLL_TUNE1);
446 dfll_writel(td, td->soc->cvb->cpu_dfll_data.tune0_low, DFLL_TUNE0);
447 dfll_writel(td, td->soc->cvb->cpu_dfll_data.tune1, DFLL_TUNE1);
447 dfll_wmb(td);
448
449 if (td->soc->set_clock_trimmers_low)
450 td->soc->set_clock_trimmers_low();
451}
452
453/*
454 * Output clock scaler helpers

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1444 rate = ULONG_MAX;
1445 opp = dev_pm_opp_find_freq_floor(td->soc->dev, &rate);
1446 if (IS_ERR(opp)) {
1447 dev_err(td->dev, "couldn't get vmax opp, empty opp table?\n");
1448 goto out;
1449 }
1450 v_max = dev_pm_opp_get_voltage(opp);
1451
448 dfll_wmb(td);
449
450 if (td->soc->set_clock_trimmers_low)
451 td->soc->set_clock_trimmers_low();
452}
453
454/*
455 * Output clock scaler helpers

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1445 rate = ULONG_MAX;
1446 opp = dev_pm_opp_find_freq_floor(td->soc->dev, &rate);
1447 if (IS_ERR(opp)) {
1448 dev_err(td->dev, "couldn't get vmax opp, empty opp table?\n");
1449 goto out;
1450 }
1451 v_max = dev_pm_opp_get_voltage(opp);
1452
1452 v = td->soc->min_millivolts * 1000;
1453 v = td->soc->cvb->min_millivolts * 1000;
1453 lut = find_vdd_map_entry_exact(td, v);
1454 if (lut < 0)
1455 goto out;
1456 td->i2c_lut[0] = lut;
1457
1458 for (j = 1, rate = 0; ; rate++) {
1459 opp = dev_pm_opp_find_freq_ceil(td->soc->dev, &rate);
1460 if (IS_ERR(opp))
1461 break;
1462 v_opp = dev_pm_opp_get_voltage(opp);
1463
1454 lut = find_vdd_map_entry_exact(td, v);
1455 if (lut < 0)
1456 goto out;
1457 td->i2c_lut[0] = lut;
1458
1459 for (j = 1, rate = 0; ; rate++) {
1460 opp = dev_pm_opp_find_freq_ceil(td->soc->dev, &rate);
1461 if (IS_ERR(opp))
1462 break;
1463 v_opp = dev_pm_opp_get_voltage(opp);
1464
1464 if (v_opp <= td->soc->min_millivolts * 1000)
1465 if (v_opp <= td->soc->cvb->min_millivolts * 1000)
1465 td->dvco_rate_min = dev_pm_opp_get_freq(opp);
1466
1467 for (;;) {
1468 v += max(1, (v_max - v) / (MAX_DFLL_VOLTAGES - j));
1469 if (v >= v_opp)
1470 break;
1471
1472 selector = find_vdd_map_entry_min(td, v);

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1485
1486 if (v >= v_max)
1487 break;
1488 }
1489 td->i2c_lut_size = j;
1490
1491 if (!td->dvco_rate_min)
1492 dev_err(td->dev, "no opp above DFLL minimum voltage %d mV\n",
1466 td->dvco_rate_min = dev_pm_opp_get_freq(opp);
1467
1468 for (;;) {
1469 v += max(1, (v_max - v) / (MAX_DFLL_VOLTAGES - j));
1470 if (v >= v_opp)
1471 break;
1472
1473 selector = find_vdd_map_entry_min(td, v);

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1486
1487 if (v >= v_max)
1488 break;
1489 }
1490 td->i2c_lut_size = j;
1491
1492 if (!td->dvco_rate_min)
1493 dev_err(td->dev, "no opp above DFLL minimum voltage %d mV\n",
1493 td->soc->min_millivolts);
1494 td->soc->cvb->min_millivolts);
1494 else
1495 ret = 0;
1496
1497out:
1498 rcu_read_unlock();
1499
1500 return ret;
1501}

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1496 ret = 0;
1497
1498out:
1499 rcu_read_unlock();
1500
1501 return ret;
1502}

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