clkgen-fsyn.c (c57d5621d2f2dc238f4b9c4d00b2a54187a75445) clkgen-fsyn.c (d5f728acd90e864251139ffc59294b336cf4b382)
1/*
2 * Copyright (C) 2014 STMicroelectronics R&D Ltd
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 */
9
10/*
11 * Authors:
12 * Stephen Gallimore <stephen.gallimore@st.com>,
13 * Pankaj Dev <pankaj.dev@st.com>.
14 */
15
16#include <linux/slab.h>
17#include <linux/of_address.h>
1/*
2 * Copyright (C) 2014 STMicroelectronics R&D Ltd
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 */
9
10/*
11 * Authors:
12 * Stephen Gallimore <stephen.gallimore@st.com>,
13 * Pankaj Dev <pankaj.dev@st.com>.
14 */
15
16#include <linux/slab.h>
17#include <linux/of_address.h>
18#include <linux/clk.h>
18#include <linux/clk-provider.h>
19
20#include "clkgen.h"
21
22/*
23 * Maximum input clock to the PLL before we divide it down by 2
24 * although in reality in actual systems this has never been seen to
25 * be used.

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335 CLKGEN_FIELD(0x308, 0x7fff, 0),
336 CLKGEN_FIELD(0x30c, 0x7fff, 0),
337 CLKGEN_FIELD(0x310, 0x7fff, 0) },
338 .sdiv = { CLKGEN_FIELD(0x304, 0xf, 20),
339 CLKGEN_FIELD(0x308, 0xf, 20),
340 CLKGEN_FIELD(0x30c, 0xf, 20),
341 CLKGEN_FIELD(0x310, 0xf, 20) },
342 .lockstatus_present = true,
19#include <linux/clk-provider.h>
20
21#include "clkgen.h"
22
23/*
24 * Maximum input clock to the PLL before we divide it down by 2
25 * although in reality in actual systems this has never been seen to
26 * be used.

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336 CLKGEN_FIELD(0x308, 0x7fff, 0),
337 CLKGEN_FIELD(0x30c, 0x7fff, 0),
338 CLKGEN_FIELD(0x310, 0x7fff, 0) },
339 .sdiv = { CLKGEN_FIELD(0x304, 0xf, 20),
340 CLKGEN_FIELD(0x308, 0xf, 20),
341 CLKGEN_FIELD(0x30c, 0xf, 20),
342 CLKGEN_FIELD(0x310, 0xf, 20) },
343 .lockstatus_present = true,
343 .lock_status = CLKGEN_FIELD(0x2f0, 0x1, 24),
344 .lock_status = CLKGEN_FIELD(0x2A0, 0x1, 24),
344 .powerup_polarity = 1,
345 .standby_polarity = 1,
346 .pll_ops = &st_quadfs_pll_c32_ops,
347 .rtbl = fs660c32_rtbl,
348 .rtbl_cnt = ARRAY_SIZE(fs660c32_rtbl),
349 .get_rate = clk_fs660c32_dig_get_rate,
350};
351

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484 spin_unlock_irqrestore(pll->lock, flags);
485}
486
487static int quadfs_pll_is_enabled(struct clk_hw *hw)
488{
489 struct st_clk_quadfs_pll *pll = to_quadfs_pll(hw);
490 u32 npda = CLKGEN_READ(pll, npda);
491
345 .powerup_polarity = 1,
346 .standby_polarity = 1,
347 .pll_ops = &st_quadfs_pll_c32_ops,
348 .rtbl = fs660c32_rtbl,
349 .rtbl_cnt = ARRAY_SIZE(fs660c32_rtbl),
350 .get_rate = clk_fs660c32_dig_get_rate,
351};
352

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485 spin_unlock_irqrestore(pll->lock, flags);
486}
487
488static int quadfs_pll_is_enabled(struct clk_hw *hw)
489{
490 struct st_clk_quadfs_pll *pll = to_quadfs_pll(hw);
491 u32 npda = CLKGEN_READ(pll, npda);
492
492 return pll->data->powerup_polarity ? !npda : !!npda;
493 return !!npda;
493}
494
495static int clk_fs660c32_vco_get_rate(unsigned long input, struct stm_fs *fs,
496 unsigned long *rate)
497{
498 unsigned long nd = fs->ndiv + 16; /* ndiv value */
499
500 *rate = input * nd;

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630 return ERR_PTR(-EINVAL);
631
632 pll = kzalloc(sizeof(*pll), GFP_KERNEL);
633 if (!pll)
634 return ERR_PTR(-ENOMEM);
635
636 init.name = name;
637 init.ops = quadfs->pll_ops;
494}
495
496static int clk_fs660c32_vco_get_rate(unsigned long input, struct stm_fs *fs,
497 unsigned long *rate)
498{
499 unsigned long nd = fs->ndiv + 16; /* ndiv value */
500
501 *rate = input * nd;

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631 return ERR_PTR(-EINVAL);
632
633 pll = kzalloc(sizeof(*pll), GFP_KERNEL);
634 if (!pll)
635 return ERR_PTR(-ENOMEM);
636
637 init.name = name;
638 init.ops = quadfs->pll_ops;
638 init.flags = CLK_IS_BASIC | CLK_GET_RATE_NOCACHE;
639 init.flags = CLK_IS_BASIC;
639 init.parent_names = &parent_name;
640 init.num_parents = 1;
641
642 pll->data = quadfs;
643 pll->regs_base = reg;
644 pll->lock = lock;
645 pll->hw.init = &init;
646

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769 struct st_clk_quadfs_fsynth *fs = to_quadfs_fsynth(hw);
770 unsigned long flags = 0;
771
772 pr_debug("%s: %s\n", __func__, __clk_get_name(hw->clk));
773
774 if (fs->lock)
775 spin_lock_irqsave(fs->lock, flags);
776
640 init.parent_names = &parent_name;
641 init.num_parents = 1;
642
643 pll->data = quadfs;
644 pll->regs_base = reg;
645 pll->lock = lock;
646 pll->hw.init = &init;
647

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770 struct st_clk_quadfs_fsynth *fs = to_quadfs_fsynth(hw);
771 unsigned long flags = 0;
772
773 pr_debug("%s: %s\n", __func__, __clk_get_name(hw->clk));
774
775 if (fs->lock)
776 spin_lock_irqsave(fs->lock, flags);
777
777 CLKGEN_WRITE(fs, nsb[fs->chan], fs->data->standby_polarity);
778 CLKGEN_WRITE(fs, nsb[fs->chan], !fs->data->standby_polarity);
778
779 if (fs->lock)
780 spin_unlock_irqrestore(fs->lock, flags);
781}
782
783static int quadfs_fsynth_is_enabled(struct clk_hw *hw)
784{
785 struct st_clk_quadfs_fsynth *fs = to_quadfs_fsynth(hw);

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1077 {
1078 .compatible = "st,stih407-quadfs660-C",
1079 .data = &st_fs660c32_C_407
1080 },
1081 {
1082 .compatible = "st,stih407-quadfs660-D",
1083 .data = &st_fs660c32_D_407
1084 },
779
780 if (fs->lock)
781 spin_unlock_irqrestore(fs->lock, flags);
782}
783
784static int quadfs_fsynth_is_enabled(struct clk_hw *hw)
785{
786 struct st_clk_quadfs_fsynth *fs = to_quadfs_fsynth(hw);

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1078 {
1079 .compatible = "st,stih407-quadfs660-C",
1080 .data = &st_fs660c32_C_407
1081 },
1082 {
1083 .compatible = "st,stih407-quadfs660-D",
1084 .data = &st_fs660c32_D_407
1085 },
1086 {
1087 .compatible = "st,stih407-quadfs660-D",
1088 .data = (void *)&st_fs660c32_D_407
1089 },
1085 {}
1086};
1087
1088static void __init st_of_create_quadfs_fsynths(
1089 struct device_node *np, const char *pll_name,
1090 struct clkgen_quadfs_data *quadfs, void __iomem *reg,
1091 spinlock_t *lock)
1092{

--- 98 unchanged lines hidden --- 		1090 {}
1091};
1092
1093static void __init st_of_create_quadfs_fsynths(
1094 struct device_node *np, const char *pll_name,
1095 struct clkgen_quadfs_data *quadfs, void __iomem *reg,
1096 spinlock_t *lock)
1097{

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