| spear6xx_clock.c (df2449aba4749fb8d04c3c1bbfad5cf8863c323b) | spear6xx_clock.c (1249979242db10d2fe1793f26e7658d94b7bf6dc) |
|---|---|
| 1/* 2 * SPEAr6xx machines clock framework source file 3 * 4 * Copyright (C) 2012 ST Microelectronics 5 * Viresh Kumar <viresh.linux@gmail.com> 6 * 7 * This file is licensed under the terms of the GNU General Public 8 * License version 2. This program is licensed "as is" without any --- 142 unchanged lines hidden (view full) --- 151 clk_register_clkdev(clk, "vco2_clk", NULL); 152 clk_register_clkdev(clk1, "pll2_clk", NULL); 153 154 clk = clk_register_fixed_factor(NULL, "wdt_clk", "osc_30m_clk", 0, 1, 155 1); 156 clk_register_clkdev(clk, NULL, "wdt"); 157 158 /* clock derived from pll1 clk */ | 1/* 2 * SPEAr6xx machines clock framework source file 3 * 4 * Copyright (C) 2012 ST Microelectronics 5 * Viresh Kumar <viresh.linux@gmail.com> 6 * 7 * This file is licensed under the terms of the GNU General Public 8 * License version 2. This program is licensed "as is" without any --- 142 unchanged lines hidden (view full) --- 151 clk_register_clkdev(clk, "vco2_clk", NULL); 152 clk_register_clkdev(clk1, "pll2_clk", NULL); 153 154 clk = clk_register_fixed_factor(NULL, "wdt_clk", "osc_30m_clk", 0, 1, 155 1); 156 clk_register_clkdev(clk, NULL, "wdt"); 157 158 /* clock derived from pll1 clk */ |
| 159 clk = clk_register_fixed_factor(NULL, "cpu_clk", "pll1_clk", 0, 1, 1); | 159 clk = clk_register_fixed_factor(NULL, "cpu_clk", "pll1_clk", 160 CLK_SET_RATE_PARENT, 1, 1); |
| 160 clk_register_clkdev(clk, "cpu_clk", NULL); 161 162 clk = clk_register_divider(NULL, "ahb_clk", "pll1_clk", 163 CLK_SET_RATE_PARENT, CORE_CLK_CFG, HCLK_RATIO_SHIFT, 164 HCLK_RATIO_MASK, 0, &_lock); 165 clk_register_clkdev(clk, "ahb_clk", NULL); 166 167 clk = clk_register_aux("uart_syn_clk", "uart_syn_gclk", "pll1_clk", 0, --- 175 unchanged lines hidden --- | 161 clk_register_clkdev(clk, "cpu_clk", NULL); 162 163 clk = clk_register_divider(NULL, "ahb_clk", "pll1_clk", 164 CLK_SET_RATE_PARENT, CORE_CLK_CFG, HCLK_RATIO_SHIFT, 165 HCLK_RATIO_MASK, 0, &_lock); 166 clk_register_clkdev(clk, "ahb_clk", NULL); 167 168 clk = clk_register_aux("uart_syn_clk", "uart_syn_gclk", "pll1_clk", 0, --- 175 unchanged lines hidden --- |